CYNSE70128-66BGC Cypress Semiconductor Corp, CYNSE70128-66BGC Datasheet - Page 17

• Manufacturer Part Number: CYNSE70128-66BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-66BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

7.4
Table 7-3 describes the command register fields.
Table 7-3. Command Register Description
Document #: 38-02040 Rev. *F
DEVE
LRAM
SRST
LDEV
HLAT
Field
TLSZ
Command Register
Range
[3:2]
[6:4]
[0]
[1]
[7]
[8]
Initial Value
000
01
0
0
0
0
Software Reset. If 1, this bit resets the device with the same effect as a hardware
reset. Internally, it generates a reset pulse lasting for eight CLK cycles. This bit
automatically resets to 0 after the reset has completed.
Device Enable. If 0, it keeps the SRAM bus (SADR, WE_L, CE_L, OE_L, and
ALE_L), SSF, and SSV signals in three-state condition and forces the cascade
interface output signals LHO[1:0] and BHO[2:0] to 0. It also keeps the DQ bus in
input mode. The purpose of this bit is to make sure that there are no bus conten-
tions when the devices power up in the system.
Table Size. The host ASIC must program this field to configure the chips into a
table of a certain size. This field affects the pipeline latency of the Search and
Learn operations as well as the Read and Write accesses to the SRAM
(SADR[23:0], CE_L, OE_L, WE_L, ALE_L, SSV, SSF, and ACK). Once
programmed, the search latency stays constant.
00: 1 device
01: Up to 8 devices
10: Up to 31 devices
11: Reserved.
00: Not supported
01: 1 device
10: 2–31 devices
11: Reserved.
Latency of Hit Signals. This field further adds latency to the SSF and SSV signals
during Search, and ACK signal during SRAM Read access by the following
number of CLK cycles.
000: 0
001: 1
010: 2
011: 3
Last Device in the Cascade. When set, this is the last device in the depth-
cascaded table and is the default driver for the SSF and SSV signals. In the event
of a search failure, the device with this bit set drives the hit signals as follows: SSF
= 0, SSV = 1.
During nonsearch cycles, the device with this bit set drives the signals as follows:
SSF = 0, SSV = 0.
Last Device on the SRAM Bus. When set, this device is the last device on the
SRAM bus in the depth-cascaded table and is the default driver for the SADR,
CE_L, WE_L, and ALE_L signals. In cycles where no CYNSE70128 device in a
depth cascaded table drives these signals, this devices drives the signals as
follows: SADR = 24’hFFFFFF, CE_L = 1, WE_L = 1, and ALE_L = 1. OE_L is
always driven by the device for which this bit is set.
Latency in number of CLK cycles with HIGH_SPEED LOW:
Latency number CLK cycles with HIGH_SPEED HIGH:
111: 7
100: 4
101: 5
110: 6
4
5
6
5
6
Description
CYNSE70128
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