CYNSE70128-66BGC Cypress Semiconductor Corp, CYNSE70128-66BGC Datasheet - Page 76

• Manufacturer Part Number: CYNSE70128-66BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-66BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

The Search command is a pipelined operation and executes at one-fourth the rate of the frequency of CLK2X for 288-bit searches
in x288-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 288-bit Search command
(measured in CLK cycles) from the CLK2X cycle that contains the C and D cycles is shown in Table 10-26.
Table 10-26. The Latency of Search from Cycles C and D to SRAM Access Cycle
The latency of a Search from command to SRAM access cycle is 4 for only a single device in the table and TLSZ = 00. In addition,
SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-27.
Table 10-27. Shift OF SSF and SSV from SADR
10.6.8
The hardware diagram of the search subsystem of eight devices is shown in Figure 10-52. The following are the parameters
programmed in the eight devices.
Note
programmed with LRAM = 1 and LDEV = 1 (device number 7 in this case). All other upstream devices must be programmed with
LRAM = 0 and LDEV = 0 (devices 0 through 6 in this case).
Figure 10-53 shows the timing diagram for a Search command in the 288-bit-configured table of eight devices for device
number 0. Figure 10-54 shows the timing diagram for a Search command in the 288-bit-configured table of eight devices for
device number 1. Figure 10-55 shows the timing diagram for a Search command in the 288-bit-configured table of eight devices
for device number 7 (the last device in this specific table). For these timing diagrams three 288-bit searches are performed
sequentially. The following Hit/Miss assumptions were made as shown in Table 10-28.
Table 10-28. Hit/Miss Assumption
Document #: 38-02040 Rev. *F
• First seven devices (devices 0–6): CFG = 1010101010101010, TLSZ = 01, HLAT = 000, LRAM = 0, and LDEV = 0.
• Eighth device (device 7): CFG = 1010101010101010, TLSZ = 01, HLAT = 000, LRAM = 1, and LDEV = 1.
. All eight devices must be programmed with the same value of TLSZ and HLAT. Only the last device in the table must be
Number of Devices
1–31 (TLSZ = 10)
1–8 (TLSZ = 01)
1 (TLSZ = 00)
Search Number
288-bit Search on Tables Configured as x288 Using up to Eight CYNSE70128 Devices
Device 2–6
Device 0
Device 1
Device 7
HLAT
000
001
010
100
101
011
110
111
Max Table Size
128K × 288 bits
496K × 288 bits
16K × 288 bits
Miss
Miss
Miss
Hit
1
Number of CLK Cycles
Miss
Miss
Miss
Hit
2
0
1
2
3
4
5
6
7
Latency in CLK Cycles
4
5
6
CYNSE70128
Miss
Miss
Miss
Miss
3
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