CYNSE70128-66BGC Cypress Semiconductor Corp, CYNSE70128-66BGC Datasheet - Page 75

• Manufacturer Part Number: CYNSE70128-66BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-66BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

The following is the sequence of operation for a single 144-bit Search command (also refer to “Commands and Command
Parameters” on page 22).
Note
The GMR index in cycle A selects a pair of GMRs that apply to DQ data in cycles A and B. The GMR index in cycle C selects a
pair of GMRs that apply to DQ data in cycles C and D.
The logical 288-bit Search operation is shown in Figure 10-51. The entire table of 288-bit entries is compared to a 288-bit word
K that is presented on the DQ bus in cycles A, B, C, and D of the command using the GMR and local mask bits. The GMR is the
288-bit word specified by the two pairs of GMRs selected by the GMR Indexes in the command’s cycles A and C. The 288-bit
word K that is presented on the DQ bus in cycles A, B, C and D of the command is compared with each entry in the table starting
at location 0. The first matching entry’s location address L is the winning address that is driven as part of the SRAM address on
SADR[23:0] lines (see “SRAM Addressing” on page 105).
entry page for a 288-bit Search (two LSBs of the matching index will be 00).
Document #: 38-02040 Rev. *F
• Cycle A: The host ASIC drives the CMDV high and applies Search command code (10) on CMD[1:0] signals. {CMD[10],
• Cycle B: The host ASIC continues to drive the CMDV high and continues to apply the command code of Search command
• Cycle C: The host ASIC drives the CMDV high and applies Search command code (10) on CMD[1:0] signals.
• Cycle D: The host ASIC continues to drive the CMDV high and applies Search command code (10) on CMD[1:0]. CMD[8:6]
CMD[5:3]} signals must be driven with the index to the GMR pair used for bits [287:144] of the data being searched. DQ[71:0]
must be driven with the 72-bit data ([287:216]) to be compared to all locations 0 in the four 72-bits-word page. The CMD[2]
signal must be driven to logic 1.
(10) on CMD[1:0]. The DQ[71:0] is driven with the 72-bit data ([215:144]) to be compared to all locations 1 in the four 72-bits-
word page.
{CMD[10],CMD[5:3]} signals must be driven with the index to the GMR pair used for bits [143:0] of the data being searched.
CMD[8:6] signals must be driven with the bits that will be driven on SADR[23:21] by this device if it has a hit. DQ[71:0] must
be driven with the 72-bit data ([143:72]) to be compared to all locations 2 in the four 72-bits-word page. The CMD[2] signal
must be driven to logic 0.
signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and the hit flag
(see page 8 for the description of SSR[0:7]). The DQ[71:0] is driven with the 72-bit data ([71:0]) to be compared to all locations
3 in the four 72-bits-word page. CMD[5:2] is ignored because the Learn instruction is not supported for x288 tables.
. For 288-bit searches, the host ASIC must supply four distinct 72-bit data words on DQ[71:0] during cycles A, B, C, and D.
DQ[71:0]
CMDV, CMD[10:0]
SSF, SSV
Location
Location
address
address
16380
16380
GMR
GMR
12
12
L
L
0
0
4
4
8
8
K
K
Figure 10-50. Hardware Diagram for a Table with One Device
287
287
287
287
BHI[2:0]
BHO[2:0]
Note
0
0
A
A
. CMD[2] = 1 signals that the Search is a x288-bit search. CMD[8:3] in this cycle is ignored.
Figure 10-51. x288 Table with One Device
CFG = 1010101010101010
(288-bit configuration)
1
1
B
B
LHO[1]
CYNSE70128
Note
2
2
. The matching address is always going to be location 0 in a four-
C
C
6
5
3
3
4
D
D
LHI
3
0
0
0
0
(First matching entry)
(First matching entry)
2
1
LHO[0]
0
SRAM
CYNSE70128
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