EVAL-AD9837SDZ Analog Devices Inc, EVAL-AD9837SDZ Datasheet - Page 4
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EVAL-AD9837SDZ
Manufacturer Part Number
EVAL-AD9837SDZ
Description
EVALUATION BOARD
Manufacturer
Analog Devices Inc
Series
-r
Specifications of EVAL-AD9837SDZ
Main Purpose
Timing, Direct Digital Synthesis (DDS)
Embedded
No
Utilized Ic / Part
AD9837
Primary Attributes
-
Secondary Attributes
Graphical User Interface
Kit Application Type
Clock & Timing
Application Sub Type
Clock Generator
Kit Contents
Software CD, USB Cable
Silicon Manufacturer
Analog Devices
Silicon Core Number
AD9837
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
AD9837
TIMING CHARACTERISTICS
VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.
Table 2.
Parameter
t
t
t
t
t
t
t
t
t
t
t
1
Timing Diagrams
1
2
3
4
5
6
7
8
9
10
11
Guaranteed by design; not production tested.
1
SDATA
FSYNC
SCLK
Limit at T
62.5
25
25
25
10
10
5
10
t
5
3
5
4
− 5
t
11
MIN
to T
t
MAX
7
D15
D14
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
t
6
t
5
MCLK
Figure 3. Serial Timing
Figure 2. Master Clock
Rev. 0 | Page 4 of 28
Description
MCLK period (f
MCLK high duration (f
MCLK low duration (f
SCLK period
SCLK high duration
SCLK low duration
FSYNC to SCLK falling edge setup time
SCLK falling edge to FSYNC rising edge time
Data setup time
Data hold time
SCLK high to FSYNC falling edge setup time
D2
t
2
t
t
4
1
t
t
3
9
D1
t
10
MCLK
= 16 MHz)
D0
MCLK
t
8
MCLK
= 16 MHz)
= 16 MHz)
D
1
5
D
1
4