MCP795W10-I/SL Microchip Technology, MCP795W10-I/SL Datasheet - Page 16

• Manufacturer Part Number: MCP795W10-I/SL
• Description: SPI GPP RTCC, 1Kb EE, 64B SRAM, WD Timer, Event Detect, ID 14 SOIC .150in TUBE
• Manufacturer: Microchip Technology

MCP795WXX/MCP795BXX
REGISTER 5-11:
DS22280B-page 16
bit 7
Legend:
R = Readable bit
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
WDTEN
R/W
Please see
bit 6
WDTEN: Watchdog Timer Enable bit
This bit is a read/write bit that is set by the user and can be cleared by the user of the hardware. This
bit is set to enable the WDT function and cleared to disable the function. This bit is cleared by the
hardware when the V
WDTIF: Watchdog Timer Interrupt Flag bit
This bit is a read/write bit that is set in hardware when the WDT times out and the WD pin is asserted.
This bit must be cleared in software to restart the WDT.
WDDEL: Watchdog Timer Delay bit
This bit is a read/write bit and is set to enable a 64-second delay before the WDT starts to count. If
this bit is set and the WDTIF bit is cleared then there will be a 64 second delay before the WDT starts
to count. This bit should be set before the WDTEN bit is set.
WDTPLS: Watchdog Timer Reset Pulse Width bit
A read/write bit that is used to select the pulse width on the WD pin when the WDT times out.
WD<3:0>: Watchdog Timer Configuration bits
Read/write bits that are used to set the WDT time-out period as below (all times are based off the
uncalibrated crystal reference). Bit 3 should be cleared and is reserved for future use:
- 0 – 122 us Pulse
- 1 – 125 ms Pulse
- 000 – 977 us
- 001 – 15.6 ms
- 010 – 62.5 ms
- 011 – 125 ms
- 100 – 1s
- 101 – 16s
- 110 – 32s
- 111 – 64s
WDTIF
R/W
WATCHDOG 0
Section 9.1.3, Watchdog Timer
bit 5
W = Writable bit
WDDEL
R/W
CC
X
supply is not present, it is not set again when V
0A
bit 4
WDTPLS
R/W
Preliminary
for more information.
bit 3
U = Unimplemented bit, read as ‘0’
WD3
R/W
WD2
R/W
bit 2
 2011-2012 Microchip Technology Inc.
CC
is present.
WD1
R/W
bit 1
bit 0
WD0
R/W