LAN8720A-CP-TR Standard Microsystems (SMSC), LAN8720A-CP-TR Datasheet - Page 20

• Manufacturer Part Number: LAN8720A-CP-TR
• Description: SMALL FOOTPRINT RMII 10/100 ETHERNET TR
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN8720A-CP-TR

• Number Of Receivers: 1
• Protocols Supported: IEEE 802.3
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Package Type: QFN
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): 0C
• Lead Free Status / Rohs Status: Compliant

Revision 1.0 (12-09-09)
3.1.2
3.1.2.1
3.1.2.2
3.1.2.3
MAC
Converter
100BASE-TX Receive
The 100BASE-TX receive data path is shown in
following subsections.
100M Receive Input
The MLT-3 from the cable is fed into the transceiver (on inputs RXP and RXN) via a 1:1 ratio
transformer. The ADC samples the incoming differential signal at a rate of 125M samples per second.
Using a 64-level quanitizer, it generates 6 digital bits to represent each sample. The DSP adjusts the
gain of the ADC according to the observed signal levels such that the full dynamic range of the ADC
can be used.
Equalizer, Baseline Wander Correction and Clock and Data Recovery
The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates
for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors,
and CAT- 5 cable. The equalizer can restore the signal for any good-quality CAT-5 cable between 1m
and 150m.
If the DC content of the signal is such that the low-frequency components fall below the low frequency
pole of the isolation transformer, then the droop characteristics of the transformer will become
significant and Baseline Wander (BLW) on the received signal will result. To prevent corruption of the
received data, the transceiver corrects for BLW and can receive the ANSI X3.263-1995 FDDI TP-PMD
defined “killer packet” with no bit errors.
The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing
unit of the DSP, selects the optimum phase for sampling the data. This is used as the received
recovered clock. This clock is used to extract the serial data from the received signal.
NRZI and MLT-3 Decoding
The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then
converted to an NRZI data stream.
Converter
NRZI
A/D
RMII 50Mhz by 2 bits
Ext Ref_CLK
NRZI
MLT-3
Converter
MLT-3
Magnetics
PLL
RMII
DATASHEET
MLT-3
by 4 bits
25MHz
125 Mbps Serial
MLT-3
6 bit Data
20
RJ45
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
Figure
Decoder
4B/5B
and BLW Correction
recovery, Equalizer
MLT-3
DSP: Timing
3.2. Each major block is explained in the
CAT-5
25MHz by
5 bits
Descrambler
and SIPO
SMSC LAN8720/LAN8720i
Datasheet