DS21348G Maxim Integrated Products, DS21348G Datasheet - Page 32

• Manufacturer Part Number: DS21348G
• Description: IC LIU T1/E1/J1 3.3V 49-BGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS21348G

• Number Of Drivers/receivers: 1/1
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 49-CSBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.1 Device Power-Up and Reset
The DS21348 will reset itself upon power-up setting all writeable registers to 00h and clear the status and
information registers. CCR3.7 (TUA1) = 0 results in the LIU transmitting unframed all ones. After the
power supplies have settled following power-up, initialize all control registers to the desired settings, then
toggle the LIRST bit (CCR3.2). At anytime, the DS21348 can be reset to the default settings by bringing
HRST (pin 29) low (level triggered) or by powering down and powering up again.
CCR4 (03H): COMMON CONTROL REGISTER 4
Table 4-2. Receive Equalizer Sensitivity Settings
(CCR4.4)
SYMBOL
JABDS
(MSB)
EGL
EGL
TPD
DJA
JAS
L2
L2
L1
L0
0
1
1
0
POSITION
(CCR1.7)
0 (E1)
0 (E1)
1 (T1)
1 (T1)
CCR4.7
CCR4.6
CCR4.5
CCR4.4
CCR4.3
CCR4.2
CCR4.1
CCR4.0
L1
ETS
-12dB (short haul)
-43dB (long haul)
-30dB (limited long haul)
-36dB (long haul)
DESCRIPTION
Line Build Out Select Bit 2. Sets the transmitter build out; see
for E1 and
Line Build Out Select Bit 1. Sets the transmitter build out; see
for E1 and
Line Build Out Select Bit 0. Sets the transmitter build out; see
for E1 and
Receive Equalizer Gain Limit. This bit controls the sensitivity of the
receive equalizer. See
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Jitter Attenuator Buffer Depth Select.
0 = 128 bits
1 = 32 bits (use for delay-sensitive applications)
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
Transmit Power-Down.
0 = normal transmitter operation
1 = powers down the transmitter and tri-states the TTIP and TRING pins
L0
SENSITIVITY
RECEIVE
Table 7-2
Table 7-2
Table 7-2
EGL
32 of 76
for T1.
for T1.
for T1.
Table
JAS
4-2.
JABDS
DJA
Table 7-1
Table 7-1
Table 7-1
(LSB)
TPD