DC1540A Linear Technology, DC1540A Datasheet - Page 49

• Manufacturer Part Number: DC1540A
• Description: LTC2978 Demoboard (includes DC1360A + DC1361A), Requires DC1613A
• Manufacturer: Linear Technology
• Series: -r

Specifications of DC1540A

• Design Resources: DC1540 Design File
• Main Purpose: Power Management, Power Supply Supervisor/Tracker/Sequencer
• Embedded: No
• Utilized Ic / Part: LTC2978
• Primary Attributes: Voltage Detector & Supervisor
• Secondary Attributes: -
• Kit Application Type: Power Management
• Application Sub Type: Power Supply Controller
• Features: Demonstration System For The LTC2978 Octal I2C / SMBus / PMBus Power Supply Monitor & Controller
• Lead Free Status / Rohs Status: Not applicable / Not applicable

WATCHDOG
A non-zero write to the MFR_WATCHDOG_T register will
reset the watchdog timer. Low-to-high transitions on the
WDI pin also reset the watchdog timer. If the timer expires,
ALERTB is asserted and the PWRGD output is optionally
deasserted and then reasserted after MFR_PWRGD_AS-
SERTION_DELAY ms. Writing 0 to either the MFR_WATCH-
DOG_T or MFR_WATCHDOG_T_FIRST registers will
disable the timer.
RESET
Holding the WDI pin low for more than t
the LTC2978 to enter the power-on reset state. Following
the subsequent rising-edge of the WDI pin, the LTC2978
will execute its power-on sequence per the user configura-
tion stored in EEPROM.
WRITE-PROTECT PIN
The WP pin allows the user to write-protect the LTC2978’s
configuration registers. The WP pin is active high, and
when asserted it overrides the WRITE_PROTECT com-
mand register. All registers are write-protected by the
WP pin except for PAGE, OPERATION, CLEAR_FAULTS,
MFR_PAGE_FF_MASK and STORE_USER_ALL.
operaTion
RESETB
will cause
OTHER OPERATIONS
Clock Sharing
Multiple LTC2978s can synchronize their clocks in an appli-
cation by connecting together the open-drain SHARE_CLK
input/outputs to a pull-up resistor as a wired AND. In this
case the fastest clock will take over and synchronize all
LTC2978s.
The LTC2978 can be configured to respond to the
SHARE_CLK pin being held low by disabling all channels
after a brief de-glitch period. When the SHARE_CLK pin
is allowed to rise, the LTC2978 will respond by beginning
a soft-start sequence.
The LTC2978 can be configured to hold SHARE_CLK
low when the unit is off for insufficient input voltage by
writing b[3] = 1 “mfr_config_vin_share_enable” of the
MFR_CONFIG_ALL register.
LTC2978

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