M95256-WMN3TP/AB STMicroelectronics, M95256-WMN3TP/AB Datasheet - Page 19

• Manufacturer Part Number: M95256-WMN3TP/AB
• Manufacturer: STMicroelectronics

M95256-DR, M95256, M95256-W, M95256-R
5.5
Figure 9.
Read from Memory Array (READ)
As shown in
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data output (Q).
If Chip Select (S) continues to be driven low, the internal address register is automatically
incremented, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
S
C
D
Q
Write Status Register (WRSR) sequence
Figure
10, to send this instruction to the device, Chip Select (S) is first driven
0
1
High Impedance
Doc ID 12276 Rev 17
2
Instruction
3
4
5
6
7
MSB
7
8
6
9 10 11 12 13 14 15
5
Register In
4
Status
3
2
1
0
AI02282D
Instructions
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