M95256-WMN3TP/AB STMicroelectronics, M95256-WMN3TP/AB Datasheet - Page 22

• Manufacturer Part Number: M95256-WMN3TP/AB
• Manufacturer: STMicroelectronics

Instructions
5.6.1
5.7
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ECC (Error Correction Code) and Write cycling
The M95256 and M95256-D devices offer an ECC (Error Correction Code) logic which
compares each 4-byte word with its associated 6 EEPROM bits of ECC. As a result, if a
single bit out of 4 bytes of data happens to be erroneous during a Read operation, the ECC
detects it and replaces it by the correct value. The read reliability is therefore much improved
by the use of this feature.
If a single byte has to be written, 4 bytes are internally modified (plus the ECC bits). That is,
the addressed byte is cycled together with the three other bytes making up the word. It is
therefore recommended to write data word by word (4 bytes) at address 4*N (where N is an
integer) in order to benefit from the larger amount of Write cycles.
The M95256 and M95256-D devices are qualified at 1 million (1 000 000) Write cycles,
using a cycling routine that writes to the device in multiples of 4-byte words.
Read Identification Page (available only in M95256-DR
devices)
The Identification Page (64 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
Reading this page is achieved with the Read Identification Page instruction (see
The Chip Select signal (S) is first driven low, the bits of the instruction byte and address
bytes are then shifted in, on Serial Data input (D). Address bit A10 must be 0, address bits
[A15:A11] and [A9:A6] are Don't Care, and the data byte pointed to by [A5:A0] is shifted out
on Serial Data output (Q). If Chip Select (S) continues to be driven low, the internal address
register is automatically incremented, and the byte of data at the new address is shifted out.
The number of bytes to read in the ID page must not exceed the page boundary, otherwise
unexpected data is read (e.g. when reading the ID page from location 24d, the number of
bytes should be less than or equal to 40d, as the ID page boundary is 64 bytes).
The read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle. The first byte addressed can be any
byte within any page.
The instruction is not accepted, and is not executed, if a write cycle is currently in progress.
Doc ID 12276 Rev 17
M95256-DR, M95256, M95256-W, M95256-R
Table
4).