CY7B9334-270JXC Cypress Semiconductor Corp, CY7B9334-270JXC Datasheet - Page 6

• Manufacturer Part Number: CY7B9334-270JXC
• Description: IC RECEIVER HOTLINK 28-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink™r
• Type: Transmitter and Receiverr

Specifications of CY7B9334-270JXC

• Package / Case: 28-PLCC
• Protocol: Fibre Channel
• Voltage - Supply: 4.5V ~ 5.5V
• Mounting Type: Surface Mount
• Product: PHY
• Supply Voltage (min): 4.5 V
• Supply Current: 0.155 A
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2908-5; CY7B9334-270JXC

Pin Description
CY7B9334 SMPTE HOTLink Receiver (continued)
CY7B9234 SMPTE HOTLink Transmitter Block Diagram Description
Input Register
The Input register holds the data to be processed by the SMPTE
HOTLink transmitter and allows the input timing to be made
consistent with standard FIFOs. The Input register is clocked by
CKW and loaded with information on the D
pins. Two enable inputs (ENA and ENN) allow the user to choose
when data is loaded in the register. Asserting ENA (Enable, active
LOW) causes the inputs to be loaded in the register on the rising edge
of CKW. If ENN (Enable Next, active LOW) is asserted when CKW
rises, the data present on the inputs on the next rising edge of CKW
will be loaded into the Input register. If neither ENA nor ENN are
asserted LOW on the rising edge of CKW, then a SYNC (K28.5)
character is sent. These two inputs allow proper timing and function
for compatibility with either asynchronous FIFOs or clocked FIFOs
without external logic, as shown in Figure 5.
In BIST mode, the Input register becomes the signature pattern
generator by logically converting the parallel Input register into a
Linear Feedback Shift Register (LFSR). When enabled, this
LFSR will generate a 511-byte sequence that includes all Data
and Special Character codes, including the explicit violation
symbols.
pseudo-random sequence that can be matched to an identical
LFSR in the Receiver.
Encoder
The Encoder transforms the input data held by the Input register
into a form more suitable for transmission on a serial interface
link. The code used is specified by ANSI X3.230 (Fibre Channel),
IBM ESCON® channel (code tables are at the end of this
datasheet), and the DVB-ASI serial interface. The eight D
inputs are converted to either a Data symbol or a Special Character,
depending upon the state of the SC/D input. If SC/D is HIGH, the data
inputs represent a control code and are encoded using the Special
Character code table. If SC/D is LOW, the data inputs are converted
using the Data code table. If a byte time passes with the inputs
disabled, the Encoder will output a Special Character Comma K28.5
(or SYNC) that will maintain link synchronization. SVS input forces the
transmission of a specified Violation symbol to allow the user to check
error handling system logic in the controller or for proprietary applica-
tions.
The 8B/10B coding function of the Encoder can be bypassed for
SMPTE systems that include an external coder or scrambler
function as part of the controller. This bypass is controlled by
setting the MODE select pin HIGH. When in bypass mode, D
(note that bit order is specified in the Fibre Channel 8B/10B code)
Document #: 38-02014 Rev. *B
BISTEN
V
V
GND
Name
CCN
CCQ
TTL In
I/O
This
pattern
Built-In Self-Test Enable. When BISTEN is LOW the Receiver awaits a D0.0 (sent once per BIST loop)
character and begins a continuous test sequence that tests the functionality of the Transmitter, the Receiver,
and the link connecting them. In BIST mode the status of the test can be monitored with RDY and RVS outputs.
In normal use BISTEN is held HIGH or wired to V
Power for output drivers.
Power for internal circuitry.
Ground.
Description
provides
a
0−7
predictable
, SC/D, and SVS
0−7
data
but
a−j
become the ten inputs to the Shifter, with D
shifted out.
Shifter
The Shifter accepts parallel data from the Encoder once each
byte time and shifts it to the serial interface output buffers using
a PLL multiplied bit clock that runs at ten (10) times the byte clock
rate. Timing for the parallel transfer is controlled by the counter
included in the Clock Generator and is not affected by signal
levels or timing at the input pins.
OutA, OutB, OutC
The serial interface PECL output buffers (ECL100K referenced
to +5V) are the drivers for the serial media. They are all
connected to the Shifter and contain the same serial data. Two
of the output pairs (OUTA± and OUTB±) are controllable by the
FOTO input and can be disabled by the system controller to force a
logical zero (i.e., “light off”) at the outputs. The third output pair
(OUTC±) is not affected by FOTO and will supply a continuous data
stream suitable for loop-back testing of the subsystem.
OUTA± and OUTB± will respond to FOTO input changes within a few
bit times. However, since FOTO is not synchronized with the trans-
mitter data stream, the outputs will be forced off or turned on at
arbitrary points in a transmitted byte. This function is intended to
augment an external laser safety controller and as an aid for Receiver
PLL testing.
In wire-based systems, control of the outputs may not be
required, and FOTO can be strapped LOW. The three outputs
are intended to add system and architectural flexibility by offering
identical serial bit-streams with separate interfaces for redundant
connections or for multiple destinations. Unneeded outputs can
be wired to V
circuitry.
Clock Generator
The clock generator is an embedded phase-locked loop (PLL)
that takes a byte-rate reference clock (CKW) and multiplies it by
ten (10) to create a bit rate clock for driving the serial shifter. The
byte rate reference comes from CKW, the rising edge of which
clocks data into the Input register. This clock must be a crystal
referenced pulse stream that has a frequency between the
minimum and maximum specified for the SMPTE HOTLink
Transmitter/Receiver pair. Signals controlled by this block form
the bit clock and the timing signals that control internal data
transfers between the Input register and the Shifter.
CC
. BISTEN has the same timing as Q
CC
to disable and power down the unused output
0−7
a
being the first bit to be
.
CY7B9234
CY7B9334
Page 6 of 36
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