MC145574APB Freescale Semiconductor, MC145574APB Datasheet - Page 79

• Manufacturer Part Number: MC145574APB
• Description: IC TRANSCEIVER ISDN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC145574APB

• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
9.2
9.3
9.4
9.5
BR0
The functions that were related to the IDL2 M FIFO of the MC145474 have been removed; writing
to this register has no effect, and reading it returns FFH. (No register shown.)
BR1
The functions that were related to the IDL2 A FIFO of the MC145474 have been removed; writing
to this register has no effect, and reading it returns FFH. (No register shown.)
BR2
BR2(7:4)
NT: Subchannel 1 (SC1) to S/T Loop — BR2(7:4) are used for multiframing. In the NT mode of opera-
tion, these four bits correspond to subchannel 1 for transmission to the TE(s). Multiframing is initiated
by the NT by setting BR7(5). When multiframing is enabled, the NT will transmit the bits in BR2(7:4)
as subchannel 1, in accordance with CCITT I.430, ETSI ETS 300012, and ANSI T1.605. BR2(7:4),
is internally polled at the start of every multiframe (this occurs every 5 ms and the device can be pro-
grammed to give an interrupt at the start of every multiframe), and its contents are interpreted as
subchannel 1. If multiframing is enabled and the contents of BR2(7:4) have not been updated, then
the subchannel is re–transmitted as is. BR2(7:4) can be updated any time between the 5 ms interrupts.
BR2(7:4) are read/write bits. Application of either a software or hardware reset resets these bits to
all 0s. Note that BR2(7) is the MSB of SC1 and BR2(4) is the LSB. Refer to Section 10 for a more
detailed description of this feature.
TE: Q Nibble to S/T Loop — BR2(7:4) are used for multiframing. In the TE mode of operation these
four bits correspond to the Q channel data for transmission to the NT. When multiframing is enabled,
the TE will transmit the bits in BR2(7:4), as Q channel data, in accordance with CCITT I.430, ETSI
ETS 300012, and ANSI T1.605. BR2(7:4) is internally polled at the start of every multiframe (this occurs
every 5 ms and the device can be programmed to give an interrupt at the start of every multiframe),
and its contents are interpreted as Q channel data. If multiframing is enabled and the contents of
BR2(7:4) have not been updated then the Q channel is re–transmitted as is. BR2(7:4) can be updated
any time between the 5 ms interrupts. BR2(7:4) are read/write bits. Application of either a software
or hardware reset sets these bits to all 1s. Note that BR2(7) is the MSB of the Q channel and BR2(4)
is the LSB. Refer to Section 10 for a more detailed description of this feature.
BR3
BR3(7:4)
NT: Q Nibble from S/T Loop — BR3(7:4) are used in the multiframing mode of operation. When
the device is configured as an NT and multiframing has been enabled, these bits correspond to the
received Q channel nibble from the TE(s). These bits are updated once every multiframe. The NT–con-
figured device can give an interrupt once every multiframe (see BR3(2) and NR4(2)) or every time
a new Q channel nibble is received. BR3(7:4) are read only bits. Application of either a hardware
BR2
BR3
TE: SC1.1
NT: SC1.1
TE: Q.1
NT: Q.1
(7)
(7)
TE: SC1.2
NT: SC1.2
TE: Q.2
NT: Q.2
(6)
(6)
TE: SC1.3
NT: SC1.3
TE: Q.3
NT: Q.3
(5)
(5)
MC145574
NT: SC1.4
TE: SC1.4
TE: Q.4
NT: Q.4
(4)
(4)
NT: Q Qual
Applicable
TE: Not
(3)
(3)
Multiframe
Interrupt
Every
(2)
(2)
(1)
(1)
(0)
(0)
9–3