SFPA8192Q1BO2TO-I-QT-223-STD Swissbit NA Inc, SFPA8192Q1BO2TO-I-QT-223-STD Datasheet - Page 26

• Manufacturer Part Number: SFPA8192Q1BO2TO-I-QT-223-STD
• Description: FLASH SSD SMART UDMA 2.5" 8GB
• Manufacturer: Swissbit NA Inc
• Series: P-120r

Specifications of SFPA8192Q1BO2TO-I-QT-223-STD

• Memory Size: 8GB
• Memory Type: FLASH
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1052-1025

Figure 9: Sustained Ultra DMA Data-Out Burst Timing
Note: Data (D15:D00) and HSTROBE signals are shown at both the device and the host to emphasize that
cable settling time as well as cable propagation delay shall not allow the data signals to be considered
stable at the device until some time after they are driven by the host.
6.3.2.4.8 Device Pausing an Ultra DMA Data-Out Burst
The device pauses an Ultra DMA Data-Out burst by following the steps lettered below. The
timing diagram is shown in Figure 10: Ultra DMA Data-Out Burst Device Pause Timing. The
timing parameters are specified in Table 22: Ultra DMA Data Burst Timing Requirements and are
described in Table 23: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
a) The host shall drive a data word onto D[15:00].
b) The host shall generate an HSTROBE edge to latch the new word no sooner than t
c)
d) The host shall repeat steps (a), (b), and (c) until the data transfer is complete or an Ultra DMA burst
a) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has
b) The device shall pause an Ultra DMA burst by negating -DDMARDY.
c)
d) If the device negates -DDMARDY within t
e) The device shall resume an Ultra DMA burst by asserting -DDMARDY.
the state of D[15:00]. The host shall generate an HSTROBE edge no more frequently than t
selected Ultra DMA mode. The host shall not generate two rising or falling HSTROBE edges more
frequently than 2t
The host shall not change the state of D[15:00] until at least t
to latch the data.
is paused, whichever occurs first.
been transferred.
The host shall stop generating HSTROBE edges within t
device shall be prepared to receive zero or one additional data words. If the device negates -
DDMARDY greater than t
prepared to receive zero, one or two additional data words. The additional data words are a result
of cable round trip delay and t
Swissbit reserves the right to change products or specifications without notice.
cyc
for the selected Ultra DMA mode.
SR
after the host has generated an HSTROBE edge, then the device shall be
RFS
timing for the host.
[e-mail]
www.swissbit.com
SR
after the host has generated an HSTROBE edge, then the
RFS
of the device negating -DDMARDY.
DVH
after generating an HSTROBE edge
P-120_data_sheet_PA-QxBO_Rev100.doc
DVS
after changing
Page
CYC
Revision: 1.00
for the
26 of 76