SFPA8192Q1BO2TO-I-QT-223-STD Swissbit NA Inc, SFPA8192Q1BO2TO-I-QT-223-STD Datasheet - Page 34

• Manufacturer Part Number: SFPA8192Q1BO2TO-I-QT-223-STD
• Description: FLASH SSD SMART UDMA 2.5" 8GB
• Manufacturer: Swissbit NA Inc
• Series: P-120r

Specifications of SFPA8192Q1BO2TO-I-QT-223-STD

• Memory Size: 8GB
• Memory Type: FLASH
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1052-1025

7.10.1 Bit 7
This bit is set to ‘1’.
7.10.2 Bit 6 (LBA)
LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address Mode (LBA). When LBA is set
to ‘0’, Cylinder/Head/Sector mode is selected. When LBA is set to’1’, Logical Block Address is selected. In
Logical Block Mode, the Logical Block Address is interpreted as follows:
7.10.3 Bit 5
This bit is set to ‘1’.
7.10.4 Bit 4 (DRV)
DRV is the drive number. When DRV is ‘0’, drive 0 is selected (Master). When DRV is ‘1’, drive 1 is selected
(Slave). The Drive is set to Drive 0 or 1 using the copy field (Drive #) of the PCMCIA Socket & Copy
configuration register.
7.10.5 Bit 3 (HS3)
When operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is bit 27 in the
Logical Block Address mode.
7.10.6 Bit 2 (HS2)
When operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is bit 26 in the
Logical Block Address mode.
7.10.7 Bit 1 (HS1)
When operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit 25 in the
Logical Block Address mode.
7.10.8 Bit 0 (HS0)
When operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit 24 in the
Logical Block Address mode.
Table 30: Drive/Head Register
7.11 Status & Alternate Status Registers
The Status & Alternate Status registers are located at addresses 1F7h [177h] and 3F6h [376h], respectively.
Offsets are 7h and Eh.
These registers return the Drive status when read by the host.
Reading the Status Register clears a pending interrupt. Reading the Auxiliary Status Register does not clear a
pending interrupt.
The Status Register should be accessed in Byte mode; in Word mode it is recommended that Alternate Status
Register is used. The status bits are described as follows
7.11.1 Bit 7 (BUSY)
The busy bit is set when only the Drive can access the command register and buffer, The host is denied
access. No other bits in this register are valid when this bit is set to ‘1’.
7.11.2 Bit 6 (RDY)
This bit indicates whether the device is capable of performing Drive operations. This bit is cleared at power
up and remains cleared until the Drive is ready to accept a command.
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
D7
1
LBA7-LBA0: Sector Number Register D7 to D0
LBA15-LBA8: Cylinder Low Register D7 to D0
LBA23-LBA16: Cylinder High Register D7 to D0
LBA27-LBA24: Drive/Head Register bits HS3 to HS0
LBA
D6
Swissbit reserves the right to change products or specifications without notice.
D5
1
[e-mail]
www.swissbit.com
DRV
D4
HS3
D3
HS2
D2
P-120_data_sheet_PA-QxBO_Rev100.doc
HS1
D1
Page
Revision: 1.00
HS0
D0
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