SFPA8192Q1BO2TO-I-QT-223-STD Swissbit NA Inc, SFPA8192Q1BO2TO-I-QT-223-STD Datasheet - Page 35

• Manufacturer Part Number: SFPA8192Q1BO2TO-I-QT-223-STD
• Description: FLASH SSD SMART UDMA 2.5" 8GB
• Manufacturer: Swissbit NA Inc
• Series: P-120r

Specifications of SFPA8192Q1BO2TO-I-QT-223-STD

• Memory Size: 8GB
• Memory Type: FLASH
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1052-1025

7.11.3 Bit 5 (DWF)
When set this bit indicates a Write Fault has occurred.
7.11.4 Bit 4 (DSC)
This bit is set when the Drive is ready.
7.11.5 Bit 3 (DRQ)
The Data Request is set when the Drive requires information be transferred either to or from the host
through the Data register. The bit is cleared by the next command.
7.11.6 Bit 2 (CORR)
This bit is set when a Correctable data error has been encountered and the data has been corrected. This
condition does not terminate a multi-sector read operation.
7.11.7 Bit 1 (IDX)
This bit is always set to ‘0’.
7.11.8 Bit 0 (ERR)
This bit is set when the previous command has ended in some type of error. The bits in the Error register
contain additional information describing the error. In case of read or write access commands that end
with an error, the address of the first sector with an error is in the command block registers. This bit is
cleared by the next command.
Table 31: Status & Alternate Status Register
7.12 Device Control Register
The Device Control register is located at address 3F6h [376h], offset Eh.
This Write-only register is used to control the Drive interrupt request and to issue an ATA soft reset to the
Drive. This register can be written even if the device is BUSY. The bits are defined as follows:
7.12.1 Bit 7 to 3
Don’t care. The host should reset this bit to ‘0’.
7.12.2 Bit 2 (SW Rst)
This bit is set to 1 in order to force the Drive to perform an AT Disk controller Soft Reset operation. This clears
Status Register and writes Diagnostic Code in Error register after a Write or Read Sector error. The Drive
remains in Reset until this bit is reset to ‘0.’
7.12.3 Bit 1 (-Ien)
When the Interrupt Enable bit is set to ‘0’, -IREQ interrupts are enabled. When the bit is set to ‘1’, interrupts
from the Drive are disabled. This bit also controls the Int bit in the Drive Configuration and Status Register.
It is set to ‘0’ at Power On.
7.12.4 Bit 0
This bit is set to ‘0’.
Table 32: Device Control Register
7.13 Drive (Drive) Address Register
The Drive Address register is located at address 3F7h [377h], offset Fh.
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
BUSY
X(0)
D7
D7
X(0)
RDY
D6
D6
Swissbit reserves the right to change products or specifications without notice.
DWF
X(0)
D5
D5
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www.swissbit.com
X(0)
DSC
D4
D4
DRQ
X(0)
D3
D3
SW Rst
CORR
D2
D2
P-120_data_sheet_PA-QxBO_Rev100.doc
-Ien
D1
D1
0
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Revision: 1.00
ERR
D0
D0
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