ADV7393BCPZ Analog Devices Inc, ADV7393BCPZ Datasheet - Page 49

• Manufacturer Part Number: ADV7393BCPZ
• Description: IC DAC VIDEO HDTV 10BIT 40LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7393BCPZ

• Design Resources: Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
• Applications: Set-Top Boxes, Video Players, Displays
• Voltage - Supply, Analog: 2.6 V ~ 3.46 V
• Voltage - Supply, Digital: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Input Format: Digital
• Output Format: Analog
• Supply Voltage Range: 1.71V To 1.89V
• Operating Temperature Range: -40°C To +85°C
• Tv / Video Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADV7393-DBRDZ - BOARD EVAL FOR ADV7393EVAL-ADV7393EBZ - BOARD EVAL FOR ADV7393 ENCODER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DESIGN FEATURES
OUTPUT OVERSAMPLING
The ADV739x includes an on-chip phase-locked loop (PLL)
that allows for oversampling of SD, ED, and HD video data. By
default, the PLL is disabled. The PLL can be enabled using
Subaddress 0x00, Bit 1 = 0.
Table 40 shows the various oversampling rates supported in the
ADV739x.
ED/HD NONSTANDARD TIMING MODE
Subaddress 0x30, Bits[7:3] = 00001
For any ED/HD input data that does not conform to the stand-
ards listed in the ED/HD standard table (Subaddress 0x30,
Bits[7:3]), the ED/HD nonstandard timing mode can be used to
interface to the ADV739x. ED/HD nonstandard timing mode
can be enabled by setting Subaddress 0x30, Bits[7:3] to 00001.
A clock signal must be provided on the CLKIN pin. HSYNC
and VSYNC must be toggled by the user to generate the
appropriate horizontal and vertical synchronization pulses on
the analog output from the encoder. Figure 63 illustrates the
Table 40. Output Oversampling Modes and Rates
000
000
000
001/010
001/010
001/010
001/010
001/010
001/010
111
111
111
1
Table 41. ED/HD Nonstandard Timing Mode Synchronization Signal Generation
Output Level Transition
b to c
c to a
a to b
c to b
1
2
X = don’t care
a = trilevel synchronization pulse level; b = blanking level/active video level; c = synchronization pulse level. See Figure 63.
If VSYNC = 1, it should transition to 0. If VSYNC = 0, it should remain at 0. If trilevel synchronization pulse generation is not required, VSYNC should always be 0.
(0x01, Bits[6:4])
Input Mode
SD
SD
SD
ED
ED
ED
HD
HD
HD
ED (at 54 MHz)
ED (at 54 MHz)
ED (at 54 MHz)
1
PLL and Oversampling
Control (0x00, Bit 1)
1
0
0
1
0
0
1
0
0
1
0
0
HSYNC
1 to 0
0
0 to 1
0 to 1
SD/ED Oversample Rate
Select (0x0D, Bit 3)
X
1
0
X
1
0
X
X
X
X
1
0
Rev. B | Page 49 of 108
various output levels that can be generated. Table 41 lists the
transitions required to generate the various output levels.
Embedded EAV/SAV timing codes are not supported in
ED/HD nonstandard timing mode.
The user must ensure that appropriate pixel data is applied to
the encoder where the blanking level is expected at the output.
Macrovision (ADV7390/ADV7392 only) and output over-
sampling are not available in ED/HD nonstandard timing mode.
The PLL must be disabled (Subaddress 0x00, Bit 1 = 1) in ED/HD
nonstandard timing mode.
a = TRILEVEL SYNCHRONIZATION PULSE LEVEL.
b = BLANKING LEVEL/ACTIVE VIDEO LEVEL.
c = SYNCHRONIZATION PULSE LEVEL.
ANALOG
OUTPUT
ADV7390/ADV7391/ADV7392/ADV7393
1
b
Figure 63. ED/HD Nonstandard Timing Mode Output Levels
HD Oversample Rate
Select (0x31, Bit 1)
X
X
X
X
X
X
X
1
0
X
X
X
c
a
BLANKING LEVEL
VSYNC
1 to 0 or 0
0 to 1
1
0
b
1
2
Oversampling Mode
and Rate
SD (2×)
SD (8×)
SD (16×)
ED (1×)
ED (4×)
ED (8×)
HD (1×)
HD (2×)
HD (4×)
ED (at 54 MHz) (1×)
ED (at 54 MHz) (4×)
ED (at 54 MHz) (8×)
ACTIVE VIDEO
b