ADV7393-DBRDZ Analog Devices Inc, ADV7393-DBRDZ Datasheet
ADV7393-DBRDZ
Specifications of ADV7393-DBRDZ
Related parts for ADV7393-DBRDZ
ADV7393-DBRDZ Summary of contents
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... Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Low Power, Chip Scale, 10-Bit SD/HD Video Encoder ADV7390/ADV7391/ADV7392/ADV7393 Fully programmable YCrCb to RGB matrix Gamma correction Programmable adaptive filter control ...
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... Register Map Access ....................................................................... 28 Register Programming ............................................................... 28 Subaddress Register (SR7 to SR0) ............................................ 28 ADV7390/ADV7391 Input Configuration ................................. 45 Standard Definition .................................................................... 45 Enhanced Definition/High Definition .................................... 45 Enhanced Definition (at 54 MHz) ........................................... 45 ADV7392/ADV7393 Input Configuration ................................. 46 Standard Definition .................................................................... 46 Enhanced Definition/High Definition .................................... 47 Enhanced Definition (at 54 MHz) ........................................... 47 Output Configuration .................................................................... 48 Design Features ............................................................................... 49 Output Oversampling ................................................................ 49 ED/HD Nonstandard Timing Mode........................................ 49 ...
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... Changes to Digital Input/Output Specifications—3.3 V Section and Table 5 ......................................................................................... 7 Added Digital Input/Output Specifications—1.8 V Section and Table 6 ................................................................................................. 7 Changes to MPU Port Timing Specifications Section, Default Conditions ............................................................................ 7 ADV7390/ADV7391/ADV7392/ADV7393 SD YPrPb Output Levels—SMPTE/EBU N10 ........................ 86 ED/HD YPrPb Output Levels ................................................... 87 SD/ED/HD RGB Output Levels ................................................ 88 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Changes to Subaddress 0xBA Section .......................................... 56 Added Sleep Mode Section............................................................ 65 Changes to Pixel and Control Port Readback Section ............... 66 Changes to Reset Mechanisms Section ........................................ 66 Added SD Teletext Insertion Section ........................................... 66 Added Figure 87 .............................................................................. 67 Added Figure 88 .............................................................................. 68 Changes to DAC Configuration Section ..................................... 68 Added Unused Pins Section .......................................................... 68 Changes to Power Supply Sequencing Section ........................... 70 Changes to Internal Test Pattern Generation Section ............... 77 Changes to SD Timing, Mode 0 (CCIR-656)— ...
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... The ADV7390/ADV7391 have an 8-bit video input port that supports SD video formats over an SDR interface and HD video formats over a DDR interface. The ADV7392/ADV7393 have a 16-bit video input port that can be configured in a variety of ways. SD RGB input is supported. All members of the family support embedded EAV/SAV timing codes, external video synchronization signals, and the I communication protocol ...
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... BYPASS YCrCb PROGRAMMABLE ED/HD FILTERS RGB MATRIX HDTV TEST SHARPNESS AND ADAPTIVE FILTER PATTERN GENERATOR CONTROL VIDEO TIMING GENERATOR HSYNC VSYNC Figure 3. ADV7392/ADV7393 (40-Lead LFCSP) Rev Page 6 of 108 AGND V SFL AA ADV7390/ADV7391 LOCK (SFL) 11-BIT DAC 1 DAC 1 16× YCrCb FILTER TO ...
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... The recommended method of bringing this value back to the ideal value is by adjusting Register 0x0B to the recommended value of 0x12. 2 Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition. ADV7390/ADV7391/ADV7392/ADV7393 Min 1.71 1.71 1 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 DIGITAL INPUT/OUTPUT SPECIFICATIONS— All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 6. Parameter Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance Output High Voltage Output Low Voltage Three-State Leakage Current Three-State Output Capacitance DIGITAL INPUT/OUTPUT SPECIFICATIONS— ...
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... Component Outputs (2×) Component Outputs (4×) RESET CONTROL RESET Low Time standard definition enhanced definition (525p/625p high definition, SDR = single data rate, DDR = dual data rate. 2 Video data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391. 3 Video control: HSYNC and VSYNC . 4 Guaranteed by characterization. 5 Guaranteed by design. ...
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... Component Outputs (2×) Component Outputs (4×) RESET CONTROL RESET Low Time standard definition enhanced definition (525p/625p high definition, SDR = single data rate, DDR = dual data rate. 2 Video data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391. 3 Video control: HSYNC and VSYNC . 4 Guaranteed by characterization. 5 Guaranteed by design. ...
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... Differential nonlinearity (DNL) measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value. For −ve DNL, the actual step value lies below the ideal step value. 3 Measured on the ADV7392/ADV7393 operating in 10-bit input mode. POWER SPECIFICATIONS ...
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... Y0 PIXEL PORT Cb0 PIXEL PORT CONTROL OUTPUTS • control output access time 13 • control output hold time 14 In addition, see Table 35 for the ADV7390/ADV7391 pixel port input configuration and Table 36 for the ADV7392/ADV7393 pixel port input configuration Cr0 Y1 Cb2 Figure 4. SD Input, 8-/10-Bit 4:2:2 YCrCb, Input Mode 000 ...
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... Figure 7. ED/HD-SDR Input, 16-Bit 4:2:2 YCrCb, Input Mode 001 CLKIN CONTROL HSYNC INPUTS VSYNC PIXEL PORT Cb0 CONTROL OUTPUTS *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2. Figure 8. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb ( HSYNC / VSYNC ), Input Mode 010 ADV7390/ADV7391/ADV7392/ADV7393 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 CLKIN* PIXEL PORT CONTROL OUTPUTS *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2. Figure 9. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 010 CLKIN CONTROL HSYNC INPUTS VSYNC PIXEL PORT t 11 CONTROL OUTPUTS Figure 10. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb ( HSYNC / VSYNC ), Input Mode 111 ...
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... PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. Figure 13. ED-DDR, 8-/10-Bit 4:2:2 YCrCb ( HSYNC / VSYNC ) Input Timing Diagram ADV7390/ADV7391/ADV7392/ADV7393 a a Rev Page 15 of 108 Y2 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Y OUTPUT HSYNC VSYNC PIXEL PORT PIXEL PORT PER RELEVANT STANDARD PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY ...
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... HSYNC VSYNC PIXEL PORT Figure 16. SD Input Timing Diagram (Timing Mode SDA t 6 SCL t 2 Figure 17. MPU Port Timing Diagram (I ADV7390/ADV7391/ADV7392/ADV7393 PAL = 264 CLOCK CYCLES NTSC = 244 CLOCK Mode) Rev Page 17 of 108 CYCLES ...
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... ADV7390/ADV7391/ADV7392/ADV7393 ABSOLUTE MAXIMUM RATINGS Table 13. 1 Parameter V to AGND DGND PGND GND_IO DD_IO AGND to DGND AGND to PGND AGND to GND_IO DGND to PGND DGND to GND_IO PGND to GND_IO Digital Input Voltage to GND_IO Analog Outputs to AGND Max CLKIN Input Frequency Storage Temperature Range ( Junction Temperature (t ...
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... PIN 1 INDICATOR ADV7392 ADV7393 TOP VIEW DGND 8 P8 (Not to Scale P10 NOTES 1. THE EXPOSED PAD SHOULD BE CONNECTED TO ANALOG GROUND (AGND). Figure 19. ADV7392/ADV7393 Pin Configuration Table 15. Pin Function Descriptions Pin No. ADV7390/ ADV7392/ ADV7390 ADV7391 ADV7393 WLCSP F5, E5, E4, C5, 31, 30 C4, B5 ADV7390/ADV7391/ADV7392/ADV7393 ...
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... D2 External Pad External Pad enhanced definition = 525p and 625p. 2 LSB = least significant bit. In the ADV7390/ADV7392, setting the LSB to 0 sets the I ADV7391/ADV7393, setting the LSB to 0 sets the I Input/ Mnemonic Output Description R I Controls the amplitudes of the DAC 1, DAC 2, and DAC 3 SET outputs. For full-drive operation (for example, into a 37.5 Ω ...
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... FREQUENCY (MHz) Figure 23. ED 8× Oversampling, Y Filter Response ADV7390/ADV7391/ADV7392/ADV7393 140 160 180 200 Figure 24. ED 8× Oversampling, Y Filter Response (Focus on Pass Band) 140 160 180 200 140 160 180 200 Rev Page 21 of 108 Y RESPONSE IN ED 8× ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Y RESPONSE IN HD 4× OVERSAMPLING MODE 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 18.5 37.0 55.5 74.0 92.5 FREQUENCY (MHz) Figure 27. HD 4× Oversampling, Y Filter Response Y PASS BAND OVERSAMPLING MODE 3.0 1.5 0 –1.5 –3.0 –4.5 –6.0 –7.5 – ...
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... FREQUENCY (MHz) Figure 34. SD Luma SSAF Filter Response MHz –2 –4 –6 –8 –10 – FREQUENCY (MHz) Figure 35. SD Luma SSAF Filter, Programmable Responses ADV7390/ADV7391/ADV7392/ADV7393 –1 180 200 0 Figure 36. SD Luma SSAF Filter, Programmable Gain 1 0 –1 –2 –3 –4 –5 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 39. SD Luma QCIF Low-Pass Filter Response 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 40. SD Chroma 3.0 MHz Low-Pass Filter Response 0 –10 –20 –30 –40 –50 –60 –70 ...
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... FREQUENCY (MHz) Figure 45. SD Chroma CIF Low-Pass Filter Response ADV7390/ADV7391/ADV7392/ADV7393 0 –10 –20 –30 –40 –50 –60 – Figure 46. SD Chroma QCIF Low-Pass Filter Response Rev Page 25 of 108 FREQUENCY (MHz) ...
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... ADV739x. The slave address depends on the device (ADV7390, ADV7391, ADV7392, or ADV7393), the operation (read or write), and the state of the ALSB pin (0 or 1). See Table 16, Figure 47, and Figure 48. The LSB sets either a read or a write operation. Logic 1 corresponds to a read operation, and Logic 0 corresponds to a write operation ...
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... START ADDR R/W ACK WRITE S SLAVE ADDR A(S) SUBADDR SEQUENCE LSB = 0 READ S SLAVE ADDR A(S) SUBADDR SEQUENCE S = START BIT A(S) = ACKNOWLEDGE BY SLAVE P = STOP BIT A(M) = ACKNOWLEDGE BY MASTER ADV7390/ADV7391/ADV7392/ADV7393 9 1– 1–7 SUBADDRESS ACK DATA ACK 2 Figure 49 Data Transfer A(S) DATA A(S) ...
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... ADV7390/ADV7391/ADV7392/ADV7393 REGISTER MAP ACCESS A microprocessor can read from or write to all registers of the ADV739x via the MPU port, except for registers that are specified as read-only or write-only registers. The subaddress register determines the register accessed by the next read or write operation. All communication through the MPU port starts with an access to the subaddress register ...
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... CSC Matrix 4 0x08 ED/HD CSC Matrix 5 0x09 ED/HD CSC Matrix Logic 0 or Logic enhanced definition = 525p and 625p. 3 Available on the ADV7392/ADV7393 (40-pin devices) only. 4 Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0x84, Bit 6 must also be enabled (SD). ADV7390/ADV7391/ADV7392/ADV7393 1 Bit Number VSYNC 0 ...
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... DAC 2 cable detect Read only Reserved Unconnected DAC autopower-down Reserved 0x13 Pixel Port P[7:0] readback (ADV7390/ADV7391) 2 Readback A P[15:8] readback (ADV7392/ADV7393) 0x14 Pixel Port P[7:0] readback (ADV7392/ADV7393) 2 Readback B 0x16 Control port Reserved readback 2 VSYNC readback HSYNC readback SFL readback Reserved 0x17 Software reset ...
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... ED/HD output standard Register 1 ED/HD input synchronization format ED/HD standard 1 Synchronization can be controlled with a combination of either HSYNC and VSYNC inputs or HSYNC and field inputs, depending on Subaddress 0x34, Bit 6. See the HD Interlace External HSYNC and VSYNC Considerations section for more information. 2 ADV7390/ADV7391/ADV7392/ADV7393 Bit Number ...
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... ED/HD CGMS enable ED/HD CGMS CRC enable 0x33 ED/HD Mode ED/HD Cr/Cb sequence Register 4 Reserved ED/HD input form Sinc compensation filter on DAC 1, DAC 2, DAC 3 Reserved ED/HD chroma SSAF filter Reserved ED/HD double buffering 1 Available on the ADV7392/ADV7393 (40-pin devices) only. Bit Number ...
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... When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so. 5 For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1). ADV7390/ADV7391/ADV7392/ADV7393 1 Bit Number 7 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Table 23. Register 0x39 to Register 0x43 SR7 to SR0 Register Bit Description 0x39 ED/HD Mode Reserved Register 7 ED/HD EIA/CEA-861B synchronization compliance Reserved 0x40 ED/HD sharpness ED/HD sharpness filter gain filter gain Value A ED/HD sharpness filter gain Value B 0x41 ED/HD CGMS ED/HD CGMS data bits ...
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... ED/HD Adaptive Filter Gain 2 0x5A ED/HD Adaptive Filter Gain 3 0x5B ED/HD Adaptive Filter Threshold A 0x5C ED/HD Adaptive Filter Threshold B 0x5D ED/HD Adaptive Filter Threshold Logic 0 or Logic 1. ADV7390/ADV7391/ADV7392/ADV7393 Bit Description 7 ED/HD Adaptive Filter Gain 1, Value A ED/HD Adaptive Filter Gain 1, 0 Value B 0 … … 1 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Table 26. Register 0x5E to Register 0x6E SR7 to SR0 Register Bit Description 0x5E ED/HD CGMS Type B ED/HD CGMS Type B Register 0 enable ED/HD CGMS Type B CRC enable ED/HD CGMS Type B header bits 0x5F ED/HD CGMS Type B ED/HD CGMS Type B Register 1 data bits 0x60 ...
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... SD square pixel mode SD VCR FF/RW sync SD pixel data valid SD active video edge control 0x83 SD Mode SD pedestal YPrPb output Register 3 SD Output Levels Y SD Output Levels PrPb SD vertical blanking interval (VBI) open SD closed captioning field control Reserved ADV7390/ADV7391/ADV7392/ADV7393 Bit Number Register Setting 0 0 NTSC 0 1 ...
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... When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so. 2 Available on the ADV7392/ADV7393 (40-pin devices) only. Bit Number 7 ...
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... SD gamma correction enable SD gamma correction curve select 0x89 SD Mode Register 8 SD undershoot limiter Reserved Reserved SD chroma delay Reserved 1 Available on the ADV7392/ADV7393 (40-pin devices) only. Table 30. Register 0x8A to Register 0x98 SR7 to SR0 Register Bit Description 0x8A SD Timing Register 0 SD slave/master mode SD timing mode ...
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... ADV7390/ADV7391/ADV7392/ADV7393 SR7 to SR0 Register Bit Description 0x8B SD Timing Register 1 SD HSYNC width Note: Applicable in master modes only, that is, Subaddress 0x8A, Bit HSYNC to VSYNC delay SD HSYNC to VSYNC rising edge delay (Mode 1 only) SD VSYNC Wwth (Mode 2 only) SD HSYNC to pixel data adjust 3 0x8C SD F Register 0 ...
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... SD brightness/WSS SD brightness value SD blank WSS data 0xA2 SD luma SSAF SD luma SSAF gain/attenuation (only applicable if Subaddress 0x87, Bit Reserved 0xA3 SD DNR 0 Coring gain border (in DNR mode, the values in brackets apply) Coring gain data (in DNR mode, the values in brackets apply) ADV7390/ADV7391/ADV7392/ADV7393 Bit Number ...
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... ADV7390/ADV7391/ADV7392/ADV7393 SR7 to SR0 Register Bit Description 0xA4 SD DNR 1 DNR threshold Border area Block size 0xA5 SD DNR 2 DNR input select DNR mode DNR block offset Logic 0 or Logic 1. Table 32. Register 0xA6 to Register 0xBB SR7 to SR0 Register Bit Description 0xA6 SD Gamma A0 SD Gamma Curve A (Point 24) ...
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... TTX Line Enable 0 Teletext on odd fields 0xCC TTX Line Enable 1 Teletext on odd fields 0xCD TTX Line Enable 2 Teletext on even fields 0xCE TTX Line Enable 3 Teletext on even fields 1 The use the teletext input pin is available on the ADV7392/ADV7393 (40-pin devices) only. ADV7390/ADV7391/ADV7392/ADV7393 1 Bit Number ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Table 34. Register 0xE0 to Register 0xF1 SR7 to 2 SR0 Register Bit Description 0xE0 Macrovision MV control bits 0xE1 Macrovision MV control bits 0xE2 Macrovision MV control bits 0xE3 Macrovision MV control bits 0xE4 Macrovision MV control bits 0xE5 Macrovision MV control bits 0xE6 Macrovision MV control bits 0xE7 ...
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... In 8-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input on Pin P7 to Pin P0 on either the rising or falling edge of CLKIN. Pin P0 is the LSB. ADV7390/ADV7391/ADV7392/ADV7393 The CrCb pixel data is also input on Pin P7 to Pin P0 on the opposite edge of CLKIN. Pin P0 is the LSB. ...
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... ADV7390/ADV7391/ADV7392/ADV7393 ADV7392/ADV7393 INPUT CONFIGURATION The ADV7392/ADV7393 support a number of different input modes. The desired input mode is selected using Subaddress 0x01, Bits[6:4]. The ADV7392/ADV7393 default to standard definition (SD) mode on power-up. Table 36 provides an overview of all possible input configurations. Each input mode is described in detail in this section. ...
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... P[15:8]/P[15:6] INTERLACED TO PROGRESSIVE 2 VSYNC HSYNC Figure 60. ED/HD-DDR Example Application 3FF Cb0 Y0 Figure 61. ED (at 54 MHz) Input Sequence (EAV/SAV) MPEG2 ADV7392/ DECODER ADV7393 54MHz CLKIN YCrCb 8/10 YCrCb P[15:8]/P[15:6] INTERLACED TO PROGRESSIVE 2 VSYNC, HSYNC Figure 62. ED (at 54 MHz) Example Application Cr0 Y1 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 OUTPUT CONFIGURATION The ADV739x supports a number of different output configurations. Table 37 to Table 39 list all possible output configurations. Table 37. SD Output Configurations RGB/YPrPb Output Select 1 SD DAC Output 1 (Subaddress 0x02, Bit 5) (Subaddress 0x82, Bit RGB output is selected, a color reversal is possible using Subaddress 0x86, Bit 7. ...
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... See Figure 63 VSYNC = 1, it should transition VSYNC = 0, it should remain trilevel synchronization pulse generation is not required, VSYNC should always be 0. ADV7390/ADV7391/ADV7392/ADV7393 various output levels that can be generated. Table 41 lists the transitions required to generate the various output levels. ...
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... ADV7390/ADV7391/ADV7392/ADV7393 HD INTERLACE EXTERNAL HSYNC AND VSYNC CONSIDERATIONS If the encoder revision code (Subaddress 0xBB, Bits[7:6 higher, the user should set Subaddress 0x02, Bit 1 to high. To ensure exactly correct timing in HD interlace modes when using HSYNC and VSYNC synchronization signals. If this bit is set to low, the first active pixel on each line is masked in HD interlace modes and the Pr and Pb outputs are swapped when using the YCrCb 4:2:2 input format ...
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... NTSC CHANGE 4 RESET ADV739x DDS. 5 REFER TO THE ADV7390/ADV7391 AND ADV7392/ADV7393 INPUT CONFIGURATION TABLES FOR PIXEL DATA PIN ASSIGNMENTS. Figure 66. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits [2:1] = 11) SD VCR FF/RW SYNC Subaddress 0x82, Bit 5 In DVD record applications where the encoder is used with a decoder, the VCR FF/RW sync control bit can be used for non- standard input video, that is, in fast forward or rewind modes ...
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... ADV7390/ADV7391/ADV7392/ADV7393 In SD Timing Mode 0 (slave option), if VBI is enabled, the blanking bit in the EAV/SAV code is overwritten possible to use VBI in this timing mode as well. If CGMS is enabled and VBI is disabled, the CGMS data is, nevertheless, available at the output. SD SUBCARRIER FREQUENCY CONTROL Subaddress 0x8C to Subaddress 0x8F The ADV739x is able to generate the color subcarrier used in CVBS and S-Video (Y-C) outputs from the input pixel clock ...
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... EAV CODE INPUT PIXELS CLOCK NTSC/PAL M SYSTEM (525 LINES/60Hz) 4 CLOCK PAL SYSTEM (625 LINES/50Hz) END OF ACTIVE VIDEO LINE Figure 67. Square Pixel Mode EAV/SAV Embedded Timing HSYNC FIELD PIXEL DATA Figure 68. Square Pixel Mode Active Pixel Timing ADV7390/ADV7391/ADV7392/ADV7393 SAV CODE ANCILLARY DATA ...
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... ADV7390/ADV7391/ADV7392/ADV7393 FILTERS Table 43 shows an overview of the programmable filters available on the ADV739x. Table 43. Selectable Filters Filter SD Luma LPF NTSC SD Luma LPF PAL SD Luma Notch NTSC SD Luma Notch PAL SD Luma SSAF SD Luma CIF SD Luma QCIF SD Chroma 0.65 MHz SD Chroma 1.0 MHz SD Chroma 1.3 MHz SD Chroma 2 ...
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... Bits[6:4]). Table 46 and Table 47 show the options available in this matrix color space conversion from RGB-in to YPrPb-out is possible on the ADV7392/ADV7393. An ED/HD color space conversion from RGB-in to YPrPb-out is not possible. Table 46. SD Color Space Conversion Options Input YCrCb YCrCb 2 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 The SD CSC matrix scalar uses the following equations × × × × × × × × × The coefficients and their default values are located in the registers shown in Table 48. Table 48. SD Manual CSC Matrix Default Values Coefficient Subaddress a1 0xBD a2 0xBE ...
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... The hue adjust value is calculated using the following equation: Hue Adjust (°) = 0.17578125° ( HCR Where HCR = the hue adjust control register (decimal). d ADV7390/ADV7391/ADV7392/ADV7393 For example, to adjust the hue by +4°, write 0x97 to the hue adjust control register. ⎛ ⎜ ⎝ ...
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... ADV7390/ADV7391/ADV7392/ADV7393 To add a –7 IRE brightness level to a PAL signal, write 0x72 to Subaddress 0xA1. 0 × Brightness Value ) = 0 × ( IRE Value × 2.075631 × (7 × 2.015631) = 0x(14.109417) ≈ 0001110b 0001110b into twos complement = 1110010b = 0x72 Table 50. Sample Brightness Control Values Setup Level Setup Level ...
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... SD Gamma Correction Curve A is programmed at Subaddress 0xA6 to Subaddress 0xAF, and SD Gamma Correction Curve B is programmed at Subaddress 0xB0 to Subaddress 0xB9. ADV7390/ADV7391/ADV7392/ADV7393 Gamma correction is performed on the luma data only. The user can choose one of two correction curves, Curve A or Curve B. Only one of these curves can be used at a time. For ED/HD gamma correction, curve selection is controlled using Subaddress 0x35, Bit 4 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 The gamma curves in Figure 74 and Figure 75 are examples only; any user-defined curve in the range from 16 to 240 is acceptable. GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT 300 250 SIGNAL OUTPUT 200 0.5 150 100 SIGNAL INPUT 100 150 LOCATION Figure 74. Signal Input (Ramp) and Signal Output for Gamma 0.5 ...
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... See Figure 77. ADV7390/ADV7391/ADV7392/ADV7393 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 FREQUENCY (MHz) FILTER B RESPONSE (Gain Kb) Figure 76. ED/HD Sharpness and Adaptive Filter Control a 1 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Figure 78. Input Signal to ED/HD Adaptive Filter Figure 79. Output Signal from ED/HD Adaptive Filter (Mode A) When the adaptive filter mode is changed to Mode B (Subaddress 0x35, Bit 6), the output shown in Figure 80 can be obtained. Figure 80. Output Signal from ED/HD Adaptive Filter (Mode B) SD DIGITAL NOISE REDUCTION Subaddress 0xA3 to Subaddress 0xA5 Digital noise reduction (DNR) is applied to the Y data only ...
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... BORDER DATA 8 × 8 PIXEL BLOCK Figure 83. SD DNR Border Area ADV7390/ADV7391/ADV7392/ADV7393 Block Size—Subaddress 0xA4, Bit 7 This bit is used to select the size of the data blocks to be processed. Setting the block size control function to Logic 1 defines a 16 pixel × 16 pixel data block, and Logic 0 defines an 8 pixel × ...
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... ADV7390/ADV7391/ADV7392/ADV7393 SD ACTIVE VIDEO EDGE CONTROL Subaddress 0x82, Bit 7 The ADV739x is able to control fast rising and falling signals at the start and end of active video to minimize ringing. When the active video edge control feature is enabled (Subaddress 0x82, Bit 7 = 1), the first three pixels and the last three pixels of the active video on the luma channel are scaled so that maximum transitions on these pixels are not possible ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Table 54 Table 55 to Table 57 ). Condition SD slave timing (Mode 1, Mode 2, or Mode 3) selected (Subaddress 0x8A[2:0]) SD slave timing (Mode 1, Mode 2, or Mode 3) selected (Subaddress 0x8A[2:0]) ED/HD timing synchronization inputs enabled (Subaddress 0x30, Bit ED/HD timing synchronization inputs enabled (Subaddress 0x30, Bit Condition ...
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... ADV7390/ADV7391/ADV7392/ADV7393 ED/HD VSYNC ED/HD Input ED/HD Sync Sync Format Control Output Enable (Subaddress (Subaddress (Subaddress 0x30, Bit 2) 0x34, Bit 2) 0x02, Bit all ED/HD standards where there is a VSYNC output, the start of the VSYNC pulse is aligned with the falling edge of the embedded VSYNC in the output video. ...
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... In accordance with the PAL WST teletext standard, teletext data should be inserted into the ADV739x at a rate of 6.9375 Mbps. On the ADV7390/ADV7391, the teletext data is inserted on the VSYNC pin. On the ADV7392/ADV7393, the teletext data can be inserted on the VSYNC or P0 pin (selectable through Subaddress 0xC9, Bit 2). ...
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... ADV7390/ADV7391/ADV7392/ADV7393 t SYNTTXOUT CVBS HSYNC 10.2µs TTX DATA TTX REQ TTX 10.2µs. SYNTTXOUT t = PIPELINE DELAY THROUGH ADV739x. PD TTX = TTX TO TTX (PROGRAMMABLE RANGE = 4 BITS [ PIXEL CLOCK CYCLES]). DEL REQ DATA t PD TTX DEL PROGRAMMABLE PULSE EDGES Figure 89. Teletext Functionality Diagram Rev Page 68 of 108 ...
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... The use of 16× (SD), 8× (ED), or 4× (HD) oversampling can remove the requirement for a reconstruction filter altogether. For applications requiring an output buffer and reconstruction filter, the ADA4430-1 and ADA4411-3 buffers should be considered. ADV7390/ADV7391/ADV7392/ADV7393 Table 58. ADV739x Output Rates Input Mode (Subaddress 0x01, Bits[6:4 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 CIRCUIT FREQUENCY RESPONSE 0 –10 –20 –30 –40 –50 GROUP DELAY (Seconds) –60 –70 –80 1M 10M 100M FREQUENCY (Hz) Figure 93. Output Filter Plot for SD, 16× Oversampling CIRCUIT FREQUENCY RESPONSE 0 –10 –20 –30 GROUP DELAY (Seconds) –40 –50 –60 –70 –80 –90 ...
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... PCB as, the ADV739x. To avoid crosstalk between the DAC outputs recommended that as much space as possible be left between the traces connected to the DAC output pins. Adding ground traces between the DAC output traces is also recommended. ADV7390/ADV7391/ADV7392/ADV7393 ADDITIONAL LAYOUT CONSIDERATIONS FOR THE WLCSP PACKAGE , PV , Due to the high pad density and 0 ...
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... C DEVICE ADDRESS IS CONFIGURABLE USING THE ALSB PIN: 2 ALSB = DEVICE ADDRESS = 0xD4 (ADV7390/ADV7392) OR 0x54 (ADV7391/ADV7393) 2 ALSB = DEVICE ADDRESS = 0xD6 (ADV7390/ADV7392) OR 0x56 (ADV7391/ADV7393) 3. THE RESISTOR CONNECTED TO THE R PIN SHOULD HAVE A 1% SET TOLERANCE. 4. THE RECOMMENDED MODE OF OPERATION FOR THE DACs IS FULL- DRIVE (R = 510Ω 37.5Ω ...
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... LOOP FILTER COMPONENTS AGND PGND DGND SHOULD BE LOCATED CLOSE TO THE EXT_LF PIN AND ON THE SAME SIDE OF THE PCB AS THE ADV7390. AGND PGND DGND ADV7390/ADV7391/ADV7392/ADV7393 V POWER DD_IO 0.1µF 0.01µF SUPPLY GND_IO GND_IO DECOUPLING PV POWER DD 0.1µF 0.01µF ...
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... ADV7390/ADV7391/ADV7392/ADV7393 COPY GENERATION MANAGEMENT SYSTEM SD CGMS Subaddress 0x99 to Subaddress 0x9B The ADV739x supports a copy generation management system (CGMS) that conforms to the EIAJ CPR-1204 and ARIB TR-B15 standards. CGMS data is transmitted on Line 20 of odd fields and Line 283 of even fields. Subaddress 0x99, Bits[6:5] control whether CGMS data is output on odd or even fields or both ...
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... REF 70% ± 10% 0mV –300mV 4T 3.128µs ± 90ns ADV7390/ADV7391/ADV7392/ADV7393 REF C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 49.1µs ± 0.5µs 2.235µs ± 20ns Figure 98. Standard Definition CGMS Waveform REF BIT 1 BIT BIT C10 C11 C12 21.2µ ...
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... ADV7390/ADV7391/ADV7392/ADV7393 +700mV 70% ± 10% 0mV –300mV 4T 4.15µs ± 60ns +700mV 70% ± 10% 0mV –300mV NOTES 1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION. +700mV 70% ±10% 0mV –300mV NOTES 1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION. REF BIT 1 BIT BIT C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 T ± ...
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... RUN-IN SEQUENCE 11.0µs ADV7390/ADV7391/ADV7392/ADV7393 Figure 105). The latter portion of Line 23 (after 42.5 μs from the falling edge of HSYNC ) is available for the insertion of video. WSS data transmission on Line 23 can be enabled using Subaddress 0x99, Bit possible to blank the WSS portion of Line 23 with Subaddress 0xA1, Bit 7. ...
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... ADV7390/ADV7391/ADV7392/ADV7393 SD CLOSED CAPTIONING Subaddress 0x91 to Subaddress 0x94 The ADV739x supports closed captioning conforming to the standard television synchronizing waveform for color trans- mission. When enabled, closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of the even fields. Closed captioning can be enabled using Subaddress 0x83, Bits[6:5] ...
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... SC F value to be written is only accepted after the F SC complete. ADV7390/ADV7391/ADV7392/ADV7393 ED/HD TEST PATTERNS The ADV739x is able to internally generate ED/HD color bar, black bar, and hatch test patterns. For ED test patterns MHz clock signal must be applied to the CLKIN pin. For HD test patterns ...
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... ADV7390/ADV7391/ADV7392/ADV7393 SD TIMING Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = The ADV739x is controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace ...
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... HSYNC and FIELD are input on the HSYNC and VSYNC pins, respectively. DISPLAY 522 523 524 525 HSYNC FIELD DISPLAY 260 261 262 263 264 HSYNC FIELD ADV7390/ADV7391/ADV7392/ADV7393 VERTICAL BLANK ODD FIELD VERTICAL BLANK 313 314 315 316 317 318 EVEN FIELD Figure 109 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 DISPLAY 622 623 624 625 HSYNC FIELD EVEN FIELD DISPLAY 309 310 311 312 HSYNC FIELD ODD FIELD Mode 1—Master Option (Subaddress 0x8A = this mode, the ADV739x can generate horizontal synchronization and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, that is, vertical retrace ...
Page 83
... VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The ADV739x automatically blanks all normally blank lines as required by the CCIR-624 standard. HSYNC and VSYNC are output on the HSYNC and VSYNC pins, respectively. HSYNC VSYNC PIXEL DATA Figure 116. SD Timing Mode 2, Even-to-Odd Field Transition (Master/Slave) ADV7390/ADV7391/ADV7392/ADV7393 VERTICAL BLANK ...
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... ADV7390/ADV7391/ADV7392/ADV7393 HSYNC VSYNC PIXEL DATA Figure 117. SD Timing Mode 2, Odd-to-Even Field Transition (Master/Slave) Mode 3—Master/Slave Option (Subaddress 0x8A = this mode, the ADV739x accepts or generates horizontal synchronization and odd/even field signals. When HSYNC is high, a transition of the field input indicates a new frame, that is, vertical retrace. The ADV739x automatically blanks all normally blank lines as required by the CCIR-624 standard ...
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... HD TIMING FIELD 1 1124 1125 VSYNC HSYNC FIELD 2 561 562 VSYNC HSYNC ADV7390/ADV7391/ADV7392/ADV7393 VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 563 564 565 566 567 568 569 Figure 120. 1080i HSYNC and VSYNC Input Timing Rev Page 85 of 108 DISPLAY 560 DISPLAY 570 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 VIDEO OUTPUT LEVELS SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10 Pattern: 100% Color Bars 700mV 300mV Figure 121. Y Levels—NTSC 700mV Figure 122. Pr Levels—NTSC 700mV Figure 123. Pb Levels—NTSC 700mV 300mV Figure 124. Y Levels—PAL 700mV Figure 125. Pr Levels—PAL 700mV Figure 126. Pb Levels— ...
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... Figure 127. EIA-770.2 Standard Output Signals (525p/625p) EIA-770.1, STANDARD FOR Y INPUT CODE 940 64 EIA-770.1, STANDARD FOR Pr/Pb 960 512 64 Figure 128. EIA-770.1 Standard Output Signals (525p/625p) ADV7390/ADV7391/ADV7392/ADV7393 OUTPUT VOLTAGE INPUT CODE 700mV 300mV OUTPUT VOLTAGE 700mV Figure 129. EIA-770.3 Standard Output Signals (1080i/720p) OUTPUT VOLTAGE INPUT CODE ...
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... ADV7390/ADV7391/ADV7392/ADV7393 SD/ED/HD RGB OUTPUT LEVELS Pattern: 100%/75% Color Bars R 700mV/525mV 300mV G 700mV/525mV 300mV B 700mV/525mV 300mV Figure 131. SD/ED RGB Output Levels—RGB Sync Disabled R 700mV/525mV 300mV 0mV G 700mV/525mV 300mV 0mV B 700mV/525mV 300mV 0mV Figure 132. SD/ED RGB Output Levels—RGB Sync Enabled ...
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... MICROSECONDS NOISE REDUCTION: 15.05dB APL NEEDS SYNC SOURCE. PRECISION MODE OFF 525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = B SLOW CLAMP TO 0.00 AT 6.72µs FRAMES SELECTED 1, 2 Figure 137. NTSC Chroma ADV7390/ADV7391/ADV7392/ADV7393 VOLTS 0.6 0.4 0.2 0 –0 NOISE REDUCTION: 0.00dB APL = 39.1% 625 LINE NTSC SLOW CLAMP TO 0.00 AT 6.72µ ...
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... ADV7390/ADV7391/ADV7392/ADV7393 VIDEO STANDARDS SMPTE 274M ANALOG WAVEFORM 4T EAV CODE INPUT PIXELS CLOCK SAMPLE NUMBER 2112 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562 SAV/EAV: LINE 563–1125 SAV/EAV: LINE 1–20; 561–583; 1124–1125 SAV/EAV: LINE 21–560; 584–1123 FOR A FRAME RATE OF 30Hz: 40 SAMPLES ...
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... Figure 144. ITU-R BT.1358 (625p) VERTICAL BLANKING INTERVAL 1 2 747 748 749 750 VERTICAL BLANKING INTERVAL FIELD 1 1124 1125 VERTICAL BLANKING INTERVAL FIELD 2 561 562 563 564 565 ADV7390/ADV7391/ADV7392/ADV7393 VERTICAL BLANK Figure 145. SMPTE 296M (720p 566 567 568 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 CONFIGURATION SCRIPTS The scripts listed in the following pages can be used to configure the ADV739x for basic operation. Certain features are enabled by default. If required for a specific application, additional features can be enabled. Table 64 lists the scripts available for SD modes of operation. Similarly, Table 99 and Table 116 list the scripts available for ED and HD modes of operation, respectively. For all scripts, only the necessary register writes are included ...
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... NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. 0x82 0xC9 Pixel data valid. RGB out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. ADV7390/ADV7391/ADV7392/ADV7393 Table 69. 8-Bit 525i YCrCb In, RGB Out Subaddress Setting 0x17 0x02 0x00 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Table 72. 10-Bit 525i YCrCb In, CVBS/Y-C Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x80 0x10 NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. 0x82 0xCB Pixel data valid ...
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... Subcarrier frequency register values for CVBS and/or S-Video (Y-C) output in 0x8D 0x55 NTSC square pixel mode (24.5454 MHz 0x8E 0x55 input clock). 0x8F 0x25 ADV7390/ADV7391/ADV7392/ADV7393 Table 81. 16-Bit NTSC Square Pixel RGB In, CVBS/Y-C Out Subaddress Setting 0x17 0x02 0x00 0x1C 0x01 0x00 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Table 84. 8-Bit 625i YCrCb In, YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x80 0x11 PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. 0x82 0xC1 Pixel data valid ...
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... Pixel data valid. RGB out. SSAF PrPb filter enabled. Active video edge control enabled. 0x88 0x10 16-bit RGB input enabled. 0x8A 0x0C Timing Mode 2 (slave). HSYNC/VSYNC synchronization. ADV7390/ADV7391/ADV7392/ADV7393 Table 94. 16-Bit 625i RGB In, YPrPb Out Subaddress Setting 0x17 0x02 0x00 0x1C 0x01 0x00 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Table 97. 8-Bit PAL Square Pixel YCrCb In (EAV/SAV), CVBS/Y-C Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x10 WLCSP required. 0x01 0x00 SD input mode. 0x80 0x11 PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. ...
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... ED-SDR input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x04 525p at 59.94 Hz. EAV/SAV synchroni- zation. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. ADV7390/ADV7391/ADV7392/ADV7393 Synchronization Format Input Color Space EAV/SAV YCrCb EAV/SAV YCrCb EAV/SAV YCrCb EAV/SAV YCrCb EAV/SAV ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Table 106. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x1C 625p at 50 Hz. EAV/SAV synchroniza- tion ...
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... DDR 1080i 10-bit DDR 1080i 16-bit SDR 1080i 16-bit SDR 1080i 16-bit SDR 1080i 16-bit SDR ADV7390/ADV7391/ADV7392/ADV7393 Table 115. 10-Bit 625p YCrCb In (EAV/SAV), RGB Out Subaddress 0x17 0x00 0x01 0x02 0x30 0x31 0x33 Synchronization Format Input Color Space EAV/SAV ...
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... ADV7390/ADV7391/ADV7392/ADV7393 Table 117. 16-Bit 720p YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x10 HD-SDR input mode. 0x30 0x2C 720p at 60 Hz/59.94 Hz. EAV/SAV syn- chronization. EIA-770.3 output levels. 0x31 0x01 Pixel data valid. 4× ...
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... HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x30 0x6C 1080i at 30 Hz/29.97 Hz. EAV/SAV syn- chronization. EIA-770.3 output levels. 0x31 0x01 Pixel data valid. 4× oversampling. ADV7390/ADV7391/ADV7392/ADV7393 Table 130. 10-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting 0x17 0x02 0x00 0x1C 0x01 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 ADV739X EVALUATION BOARD To accommodate evaluation of the ADV7390/ADV7391/ ADV7392/ADV7393, Analog Devices provides a two-board solution. The ADV739x evaluation platform front-end board contains an Analog Devices decoder (ADV7403) and an FPGA. The back-end board (where the actual ADV739x is attached) is connected to the front-end board through a connector. ...
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... OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE ADV7390/ADV7391/ADV7392/ADV7393 5.00 BSC SQ 0.60 MAX 24 0.50 BSC TOP 4.75 VIEW BSC SQ 0.50 0.40 17 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM ...
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... Macrovision-enabled ICs require the buyer approved licensee (authorized buyer) of ICs that are able to output Macrovision Rev 7.1.L1-compliant video. AUTOMOTIVE PRODUCTS The ADV7392W and ADV7393W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully ...
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... NOTES ADV7390/ADV7391/ADV7392/ADV7393 Rev Page 107 of 108 ...
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... ADV7390/ADV7391/ADV7392/ADV7393 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2006-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06234-0-7/10(B) Rev Page 108 of 108 ...