Z8623012PSG Zilog, Z8623012PSG Datasheet - Page 25

• Manufacturer Part Number: Z8623012PSG
• Description: IC SMART V-CHIP W/2ND I2C 18-DIP
• Manufacturer: Zilog
• Type: Video Decoderr

Specifications of Z8623012PSG

• Applications: Set-Top Boxes, TV
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Processor Series: Z8623x
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: CMOS
• Maximum Clock Frequency: 12 MHz
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / Rohs Status: Details

6.
6.1 R
6.1.1 Serial Status Register
6.1.2 Configuration Register
PS000401-TVC0699
CONTROL REGISTERS
EGISTERS
S
UMMARY
R
Information controlling the setup and operation of the Z86230 are maintained in
several registers. The user may read or alter the contents of these registers as
required.
All register diagrams indicated in this section incorporate the following conven-
tions, unless otherwise noted:
•
•
T
D
be used as an indication of the presence of a video signal.
D
D
not read out and new data is written over it.
D
Reserved.
D
D
D
D
NOP
T
Bit
R/W
Bit
R/W
EGISTERS
ABLE
ABLE
0
1
2
3
4
5
6
7
–LOCK.
–FLD.
–ROVR.
–INTR.
–WOVR.
-Res.
-DAV.
–RDY.
R = Read, W = Write, X = Indeterminate, and res = Reserved
All register bits marked as res must be set to Low(0)
,
RESET
11. S
12. C
Reserved.
Signals the current video field. Low = Field 2, High = Field 1.
Active High, indicating that data is available to be read out.
Active High, indicating that the port input buffer is empty. Only the
S
Active High, indicating that an interrupt other than
Active High, indicating that the internal sync circuits are locked. May
UMMARY
Active High, indicating that the data available in the output buffer is
Active High, indicating a serial input data overrun.
ERIAL
ONFIGURATION
and
Z86230—PRELIMINARY
S
READ
RDY
TATUS
res
7
R
7
R
instructions may be sent if
R
DAV
R
res
EGISTER
R
R
6
6
EGISTER
res
res
R
R
5
5
(A
(A
DDRESS
DDRESS
WOVR
res
R
R
4
4
N
= 00h)
OT
INTR
res
R
R
RDY
R
3
3
EQUIRED
is Low.
ROVR
R/W
res
R
2
2
)
C
DAV
ONTROL
is pending.
FLD
res
R
R
1
1
R
EGISTERS
LOCK
TVS
R/W
R
0
0
25