ADV7195KS Analog Devices Inc, ADV7195KS Datasheet - Page 27

• Manufacturer Part Number: ADV7195KS
• Description: IC DAC VID-HDTV 3CH-11BIT 52MQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7195KS

• Rohs Status: RoHS non-compliant
• Applications: HDTV, MPEG, Image Processing
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 52-MQFP, 52-PQFP
• Adc/dac Resolution: 11b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 52
• For Use With: EVAL-ADV7195EB - BOARD EVAL FOR ADV7195
• Lead Free Status / RoHS Status: Not Compliant

MODE REGISTER 1
MR1 (MR17–MR10)
(Address (SR4-SR0) = 01H)
Figure 51 shows the various operations under the control of
Mode Register 1.
MR1 BIT DESCRIPTION
Pixel Data Enable (MR10)
When this bit is set to “0,” the pixel data input to the ADV7195
is blanked such that a black screen is output from the DACs.
When this bit is set to “1,” pixel data is accepted at the input
pins and the ADV7195 outputs to the standard set in “Output
Standard Selection” (MR01–00). This bit also must be set to
“1” to enable output of the test pattern signals.
Input Format (MR11)
It is possible to input data in 4:2:2 format or in 4:4:4
HDTV format.
Test Pattern Enable (MR12)
Enables or disables the internal test pattern generator.
BE WRITTEN
ZERO MUST
TO THIS BIT
MR17
MR07
MR07
MR06
0
1
BE WRITTEN
MR17–MR15
ZERO MUST
TO THIS BIT
DV POLARITY
MR16
ACTIVE HIGH
ACTIVE LOW
MR06
MR05
STANDARD
0
1
INPUT
MR15
MR05
1080I
720P
MR14
0
1
VBI OPEN
BE WRITTEN
MR14
ZERO MUST
TO THIS BIT
DISABLE
ENABLE
MR04
MR04
MR13
0
1
TEST PATTERN
HATCH/FRAME
HATCH
FIELD/FRAME
Test Pattern Hatch/Frame (MR13)
If this bit is set to “0,” a crosshatch test pattern is output from
the ADV7195. The crosshatch test pattern can be used to test
monitor convergence.
If this bit is set to “1,” a uniform colored frame/field test pattern
is output from the ADV7195.
The color of the lines or the frame/field is white by default but
can be programmed to be any color using the Color Y, Color
Cr, Color Cb registers.
VBI Open (MR14)
This bit enables or disables the facility of VBI data insertion
during the Vertical Blanking Interval.
For this purpose Lines 7–20 in 1080i and Lines 6–25 in 720p
can be used for VBI data insertion.
Reserved (MR15–MR17)
A “0” must be written to these bits.
MR13
MR03
MR03
0
0
1
1
INPUT CONTROL SIGNALS
MR12
TEST PATTERN
0
1
ENABLE
MR02
MR12
0
1
0
1
MR01 MR00
DISABLE
ENABLE
MR02
OUTPUT STANDARD SELECTION
0
0
1
1
MR11
0
1
HSYNC/VSYNC/DV
EAV/SAV
TSYNC/SYNC/DV
RESERVED
INPUT FORMAT
0
1
0
1
4:4:4 Y CR CB
4:2:2 Y CR CB
MR11
MR01
EIA770.3
RESERVED
FULL I/P RANGE
RESERVED
MR10
0
1
PIXEL DATA
MR10
ENABLE
MR00
DISABLE
ENABLE
ADV7195