SAA7129H/V1,518 NXP Semiconductors, SAA7129H/V1,518 Datasheet - Page 29
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SAA7129H/V1,518
Manufacturer Part Number
SAA7129H/V1,518
Description
IC DIGITAL VIDEO DECODER 44QFP
Manufacturer
NXP Semiconductors
Type
Video Encoderr
Datasheet
1.SAA7129HV1557.pdf
(55 pages)
Specifications of SAA7129H/V1,518
Voltage - Supply, Analog
3.1 V ~ 3.5 V
Voltage - Supply, Digital
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
44-MQFP, 44-PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Other names
935262601518
SAA7129HB-T
SAA7129HB-T
SAA7129HB-T
SAA7129HB-T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SAA7129H/V1,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
9397 750 14325
Product data sheet
Table 53:
Table 54:
Table 55:
Bit
4
3
2
1
0
SRCV11
0
0
1
1
Bit
7 to 0
Symbol
HTRIG[7:0] These are the 8 LSBs of the 11-bit code that sets the horizontal trigger
Subaddress 6Bh
Selection of the signal type on pin RCV1
Subaddress 6Ch
SRCV10
0
1
0
1
Symbol
ORCV1
PRCV1
CBLF
ORCV2
PRCV2
Rev. 03 — 9 December 2004
RCV1
VS
FS
FSEQ
-
Description
phase related to the signal on RCV1 or RCV2 input. The 3 MSBs are held
in subaddress 6Dh; see
1727 (FISE = 0) are not allowed. Increasing HTRIG[10:0] decreases
delays of all internally generated timing signals. Reference mark: analog
output horizontal sync (leading slope) coincides with active edge of RCV
used for triggering at HTRIG[10:0] = 4Fh (79).
Description
0 = pin RCV1 is switched to input; default state after reset,
1 = pin RCV1 is switched to output.
0 = polarity of RCV1 as output is active HIGH, rising edge is taken
when input; default state after reset,
1 = polarity of RCV1 as output is active LOW, falling edge is taken
when input.
when CBLF = 0:
when CBLF = 1:
0 = pin RCV2 is switched to input; default state after reset,
1 = pin RCV2 is switched to output.
0 = polarity of RCV2 as output is active HIGH, rising edge is taken
when input, respectively; default state after reset,
1 = polarity of RCV2 as output is active LOW, falling edge is taken
when input, respectively.
…continued
If ORCV2 = 1, pin RCV2 provides an HREF signal (horizontal
reference pulse that is defined by RCV2S and RCV2E, also during
vertical blanking interval); default state after reset
If ORCV2 = 0 and bit SYMP = 0, signal input to RCV2 is used for
horizontal synchronization only (if TRCV2 = 1); default state after
reset.
If ORCV2 = 1, pin RCV2 provides a ‘composite-blanking-not’ signal,
for example a reference pulse that is defined by RCV2S and
RCV2E, excluding vertical blanking interval, which is defined by FAL
and LAL
If ORCV2 = 0 and bit SYMP = 0, signal input to RCV2 is used for
horizontal synchronization (if TRCV2 = 1) and as an internal
blanking signal.
Function
Vertical Sync each field; default state after reset
Frame Sync (odd/even).
Field Sequence, vertical sync every fourth field (PAL = 0),
eighth field (PAL = 1) or twelfth field (SECAM = 1).
not applicable
SAA7128H; SAA7129H
Table
56. Values above 1715 (FISE = 1) or
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Digital video encoder
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