UDA1380TTN2 NXP Semiconductors, UDA1380TTN2 Datasheet - Page 39
UDA1380TTN2
Manufacturer Part Number
UDA1380TTN2
Description
Manufacturer
NXP Semiconductors
Datasheet
1.UDA1380TTN2.pdf
(68 pages)
Specifications of UDA1380TTN2
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NXP Semiconductors
11.8
Table 38 Register address 12H
Table 39 Description of register bits
Table 40 Flat/minimum/maximum setting bits
2004 Apr 22
Symbol
Default
Symbol
Default
15 and 14
13 and 12
Stereo audio coder-decoder
for MD, CD and MP3
7 and 6
5 and 4
VC2_7
VC1_7
11 to 8
3 to 0
BIT
BIT
BIT
M1
1
1
0
0
1
1
:
Mode, bass boost and treble
M[1:0]
TRL[1:0]
BBL[3:0]
BBR[3:0]
−
TRR[1:0]
SYMBOL
VC2_6
VC1_6
M1
M0
15
1
1
0
7
−
0
0
1
0
1
:
Flat/minimum/maximum setting. A 2-bit value to program the mode of the sound
processing filters of bass boost and treble. Default value 00, see Table 40.
Treble setting left. A 2-bit value to program the mode of the sound processing filter of
treble. The used setting depends on the bits M1 and M0. Default value 00, see Table 41.
Bass boost setting left. A 4-bit value to program the bass boost setting, which can be set
for left and right independently. The used set depends on the bits M1 and M0. Default
value 0000, see Table 42.
default value 00
Treble setting right. A 2-bit value to program the mode of the sound processing filter of
treble. Default value 00, see Table 41.
Bass boost setting right. A 4-bit value to program the bass boost setting, which can be
set for left and right independently. The used set depends on the mode bits. Default
value 0000, see Table 42.
VC2_5
VC1_5
M0
14
1
1
0
6
−
0
:
VC2_4
VC1_4
TRR1
TRL1
13
0
1
0
5
0
:
VC2_3
VC1_3
TRR0
TRL0
12
39
0
1
0
4
0
:
DESCRIPTION
flat (default)
maximum
minimum
minimum
VC2_2
VC1_2
BBR3
Mode
BBL3
11
1
1
0
3
0
:
VC2_1
VC1_1
BBR2
BBL2
10
0
0
0
2
0
:
VC2_0
VC1_0
BBR1
BBL1
Product specification
0
0
9
0
1
0
:
UDA1380
VOLUME
BBR0
BBL0
(dB)
−∞
−∞
8
0
0
0
:
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