UDA1380TTN2 NXP Semiconductors, UDA1380TTN2 Datasheet - Page 49
UDA1380TTN2
Manufacturer Part Number
UDA1380TTN2
Description
Manufacturer
NXP Semiconductors
Datasheet
1.UDA1380TTN2.pdf
(68 pages)
Specifications of UDA1380TTN2
Lead Free Status / Rohs Status
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NXP Semiconductors
11.17 Decimator read-out
Table 67 Register address 28H
Table 68 Description of register bits
2004 Apr 22
Symbol
Symbol
Stereo audio coder-decoder
for MD, CD and MP3
15 to 5
BIT
BIT
BIT
BIT
4
3
2
1
0
4
3
2
1
0
SDETR1
SDETL1
MUTE_STATE_M
MUTE_STATE_CH2
MUTE_STATE_CH1
−
AGC_STAT
−
MT_ADC_STAT
−
OVERFLOW
15
−
7
−
SYMBOL
SYMBOL
14
−
6
−
not used
AGC gain status. A 1-bit value which signals whether the AGC gain exceeds
8 dB or not. Only valid when the AGC is switched on. When this bit is logic 0:
AGC gain <8 dB. When this bit is logic 1: AGC gain ≥8 dB.
not used
Decimator mute. A 1-bit value which signals whether the decimator has
reached mute or not. When this bit is logic 0: decimator has not muted. When
this bit is logic 1: decimator has muted.
not used
Digital output overflow detection. A 1-bit value which signals whether the
digital output amplitude exceeds −1.16 dB or not. When this bit is logic 0: no
overflow detected (read-out). When this bit is logic 1: overflow detected
(read-out).
Interpolator silence detect channel 1 right. When this bit is logic 0:
interpolator on channel 1 right input has detected no silence. When this bit is
logic 1: interpolator on channel 1 right input has detected silence.
Interpolator silence detect channel 1 left. When this bit is logic 0:
interpolator on channel 1 left input has detected no silence. When this bit is
logic 1: interpolator on channel 1 left input has detected silence.
Interpolator muting. A 1-bit value which signals whether the interpolator has
reached mute or not. When this bit is logic 0: interpolator is not muted. When
this bit is logic 1: interpolator is muted.
Interpolator muting channel 2. When this bit is logic 0: interpolator channel 2
is not muted. When this bit is logic 1: interpolator channel 2 is muted.
Interpolator muting channel 1. When this bit is logic 0: interpolator channel 1
is not muted. When this bit is logic 1: interpolator channel 1 is muted.
13
−
5
−
AGC_STAT
12
−
4
49
11
−
3
−
DESCRIPTION
DESCRIPTION
MT_ADC_STAT
10
−
2
9
1
−
−
Product specification
UDA1380
OVERFLOW
8
−
0
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