PCA9698DGG,512 NXP Semiconductors, PCA9698DGG,512 Datasheet - Page 37

• Manufacturer Part Number: PCA9698DGG,512
• Description: IC I/O EXPANDER I2C 40B 56TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9698DGG,512

• Package / Case: 56-TSSOP
• Interface: I²C
• Number Of I /o: 40
• Interrupt Output: Yes
• Frequency - Clock: 1MHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCA9698
• Number Of Lines (input / Output): 40.0 / 40.0
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 500 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5.5 V
• Logic Type: I2C Bus
• Maximum Clock Frequency: 1 MHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 40.0
• Number Of Output Lines: 40.0
• Output Current: 50 mA
• Output Voltage: 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM6281 - DAUGHTER CARD PCA9698 FOR OM6275
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3241-5; 935278614512; PCA9698DGG

NXP Semiconductors
12. Dynamic characteristics
Table 15.
[1]
PCA9698
Product data sheet
Symbol Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
Port timing
t
t
t
t
t
Interrupt timing
t
t
Reset
t
t
t
SCL
BUF
HD;STA
SU;STA
SU;STO
HD;DAT
VD;ACK
VD;DAT
SU;DAT
LOW
HIGH
f
r
SP
en
dis
v(Q)
su(D)
h(D)
v(INT_N)
rst(INT_N)
w(rst)
rec(rst)
rst
t
VD;ACK
SCL clock frequency
bus free time between a
STOP and START
condition
hold time (repeated)
START condition
set-up time for a repeated
START condition
set-up time for STOP
condition
data hold time
data valid acknowledge
time
data valid time
data set-up time
LOW period of the SCL
clock
HIGH period of the SCL
clock
fall time of both SDA and
SCL signals
rise time of both SDA and
SCL signals
pulse width of spikes that
must be suppressed by the
input filter
enable time
disable time
data output valid time
data input set-up time
data input hold time
valid time on pin INT
reset time on pin INT
reset pulse width
reset recovery time
reset time
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
Dynamic characteristics
Conditions
output
output
All information provided in this document is subject to legal disclaimers.
40-bit Fm+ I
Rev. 3 — 3 August 2010
[4][6]
[4][6]
[3]
[1]
[2]
[7]
Standard-mode
Min
250
100
250
100
300
4.7
4.0
4.7
4.0
0.1
4.7
4.0
0
0
4
0
-
-
-
-
-
-
-
-
I
2
C-bus
2
C-bus advanced I/O port with RESET, OE and INT
1000
Max
3.45
100
300
250
50
80
40
4
4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
20 + 0.1C
20 + 0.1C
Fast-mode I
Min
100
100
250
100
1.3
0.6
0.6
0.6
0.1
1.3
0.6
75
0
0
4
0
-
-
-
-
-
-
b
b
[5]
[5]
2
C-bus Fast-mode Plus
Max
400
300
300
250
0.9
50
80
40
4
4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.26
0.26
0.26
0.05
0.26
Min
100
250
100
0.5
0.5
75
50
PCA9698
4
0
0
0
-
-
-
-
-
-
-
-
© NXP B.V. 2010. All rights reserved.
I
2
C-bus
1000
Max
0.45
450
120
120
250
50
80
40
4
4
-
-
-
-
-
-
-
-
-
-
-
-
-
37 of 48
ns
ns
ns
ns
ns
ns
ns
Unit
kHz
μs
μs
μs
μs
ns
μs
ns
μs
μs
ns
ns
ns
ns
ns
μs
μs