MIC74YQS TR Micrel Inc, MIC74YQS TR Datasheet - Page 11

• Manufacturer Part Number: MIC74YQS TR
• Description: IC I/O EXPANDER I2C 8B 16QSOP
• Manufacturer: Micrel Inc

Specifications of MIC74YQS TR

• Interface: I²C, SMBus
• Number Of I /o: 8
• Interrupt Output: Yes
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency - Clock: -
• Other names: MIC74YQSTR; MIC74YQSTR

Application Information
Bit Transfer
The data received on the DATA pin must be stable
during the high period of the clock.
Data can change state only when the CLK line is low.
Refer to Figure 3.
Start and Stop Conditions
Two unique bus situations define “start” and “stop”
conditions. A high-to-low transition of the DATA line
while CLK is high indicates a start condition. A low-to-
high transition of the DATA line while CLK is high
defines a stop condition. See Figure 4.
Acknowledge and Not Acknowledge
The acknowledge related clock pulse is generated by the
master. The transmitter releases the DATA line (high)
during the acknowledge clock cycle.
In order to acknowledge (ACK) a byte, the receiver must
pull the DATA line low during the high period of the clock
pulse according the bus timing specifications. A slave
device that wishes to not acknowledge a byte must let
the DATA line remain high during the acknowledge clock
pulse. See Figure 6.
Micrel, Inc.
October 2006
DATA
Figure 3. Acceptable Bit Transfer Conditions
CLK
DATA
CLK
Start
Data Change Allowed
MSB
1
Data Stable,
Data Valid
2
3
4
Figure 5. Serial Byte Format
5
6
7
LSB
8
ACK
11
9
Start (S) and stop (P) conditions are always generated
by the bus master (host). After a start condition, the bus
is considered to be busy. The bus becomes free again
after a certain time following a stop condition or after
both CLK and DATA lines remain high for more than
50µs.
Serial Byte Format
Every byte consists of 8 bits. Each byte transferred on
the bus must be followed by an acknowledge bit. Bytes
are transferred with the MSB (most significant bit) first.
See Figure 5.
(Slave MIC74)
1
Byte Complete
2
Figure 6. Acknowledge and Not Acknowledge
(Host)
DATA
DATA
DATA
3
CLK
CLK
4
Figure 4. Start and Stop Definitions
5
Start
6
7
MSB
1
8
ACK
2
9
3
4
StoP
5
6
7
LSB
8
M9999-101006
StoP
ACK
9
NAK (high)
ACK (low)
MIC74