IMQ82C55AZ96 Intersil, IMQ82C55AZ96 Datasheet - Page 3

• Manufacturer Part Number: IMQ82C55AZ96
• Description: IC I/O EXPANDER 24B 44MQFP
• Manufacturer: Intersil

Specifications of IMQ82C55AZ96

• Interface: Programmable
• Number Of I /o: 24
• Interrupt Output: No
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-MQFP, 44-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency - Clock: -

Pin Description
Functional Diagram
SYMBOL
PB0-PB7
PC0-PC7
PA0-PA7
RESET
D0-D7
A0-A1
GND
V
WR
RD
CS
CC
SUPPLIES
POWER
BIDIRECTIONAL
RESET
D7-D0
DATA BUS
TYPE
WR
RD
CS
A1
A0
I/O
I/O
I/O
I/O
I
I
I
I
I
V
GROUND
DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus.
RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode.
CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU
communications.
READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus.
WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A.
ADDRESS: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three
ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus
A0, A1.
PORT A: 8-bit input and output port.
PORT B: 8-bit input and output port.
PORT C: 8-bit input and output port.
CC
3
: The +5V power supply pin. A 0.1µF capacitor between V
DATA BUS
CONTROL
BUFFER
+5V
GND
WRITE
LOGIC
READ
MS82C55A, MQ82C55A, MP82C55A
FIGURE 1. FUNCTIONAL DIAGRAM
CONTROL
CONTROL
GROUP A
GROUP B
INTERNAL
DATA BUS
8-BIT
DESCRIPTION
CC
and GND is recommended for decoupling.
GROUP A
GROUP A
GROUP B
GROUP B
PORT A
PORT C
PORT B
UPPER
PORT C
LOWER
(8)
(4)
(8)
(4)
PC7-PC4
PC3-PC0
PB7-PB0
PA7-PA0
I/O
I/O
I/O
I/O
June 15, 2006
FN6140.2