X96010V14IZ Intersil, X96010V14IZ Datasheet - Page 24

• Manufacturer Part Number: X96010V14IZ
• Description: IC SENSOR CONDITIONER 14-TSSOP
• Manufacturer: Intersil
• Type: Sensor Conditionerr

Specifications of X96010V14IZ

• Input Type: Voltage
• Output Type: Voltage
• Interface: 2-Wire
• Current - Supply: 15mA
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The four registers Control 1 through 4, have a nonvol-
atile and a volatile cell for each bit. At power-up, the
content of the nonvolatile cells is automatically
recalled and written to the volatile cells. The content of
the volatile cells controls the X96010’s functionality. If
bit NV1234 in the Control 0 register is set to “1”, a
Write operation to these registers writes to both the
volatile and nonvolatile cells. If bit NV1234 in the Con-
trol 0 register is set to “0”, a Write operation to these
registers only writes to the volatile cells. In both cases
the newly written values effectively control the
X96010, but in the second case, those values are lost
when the part is powered down.
If bit NV1234 is set to “0”, a Byte Write operation to
Control registers 0 or 5 causes the value in the nonvol-
atile cells of Control registers 1 through 4 to be
recalled into their corresponding volatile cells, as dur-
ing power-up. This doesn’t happen when the WP pin is
LOW, because Write Protection is enabled. It is gener-
ally recommended to configure Control registers 0 and
5 before writing to Control registers 1 through 4.
Figure 19. Example: Writing 12 bytes to a 16-byte page starting at location 11.
Figure 20. Writing to Control Registers 1, 2, 3, and 4
Signal at SDA
Signals from
Signals from
the Master
the Slave
Address = 0
24
S
a
r
t
t
7 bytes
1
0
1
Address
Slave
0
Address = 6
0
Write
C
A
K
1
0
Byte = 81h
Address
0
X96010
0
0 0
0
Address = 7
Address Pointer
Ends Up Here
1
When reading any of the control registers 1, 2, 3, or 4,
the Data Bytes are always the content of the corre-
sponding nonvolatile cells, even if bit NV1234 is "0"
(See “Control and Status Register Format”).
Read Operation
A Read operation consist of a three byte instruction
followed by one or more Data Bytes (See Figure 21).
The master initiates the operation issuing the following
sequence: a START, the Slave Address byte with the
R/W bit set to “0”, an Address Byte, a second START,
and a second Slave Address byte with the R/W bit set
to “1”. After each of the three bytes, the X96010
responds with an ACK. Then the X96010 transmits
Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eigth bit of
each byte. The master terminates the read operation
(issuing a STOP condition) following the last bit of the
last Data Byte (See Figure 21).
A
C
K
Data Byte for
Control 1
Address = 11
Four Data Bytes
5 bytes
5 bytes
C
A
K
Address = 15
Data Byte for
Control 4
A
C
K
S
o
p
t
October 25, 2005
FN8214.1