AD9898KCP-20 Analog Devices Inc, AD9898KCP-20 Datasheet - Page 41

• Manufacturer Part Number: AD9898KCP-20
• Description: IC CCD SIGNAL PROC/GEN 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9898KCP-20

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 3
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

VSUB CONTROL
The CCD readout bias (VSUB) can be programmed to accom-
modate different CCDs. VSUB ON and OFF toggle positions
and polarity are controlled using VSUBTOG (Addr 0x0D) and
VSUBPOL (Addr 0x0D) registers, respectively, as described in
Table XXIV. Since the VSUBTOG is an 11-bit register, the
VSUB ON position is programmable within any line. Figure 43
shows an example of controlling VSUB using these registers.
Register
Name
VSUBPOL 1
VSUBTOG 11
REV. 0
Bit
Width Type
WRITES
SERIAL
VSUB
Table XXIV. VSUB Registers
HD
VD
Register Range
Control
Control
1
2
(Lines) Description
0–2048 VSUB Toggle Position
2 LINES
3
(0 = Low, 1 = High)
Figure 43. VSUB Timing Example
–41–
VSUB Placement and Polarity
Figure 43 shows the sequence of events for programming the
VSUB ON and OFF toggle positions and polarity.
1. Program VSUBTOG = 2 and VSUBPOL = 1.
2. Since VSUBTOG and VSUBPOL are VD synchronous type
3. VSUB will be asserted high after two HD cycles.
4. Program VSUBTOG = 3 and VSUBPOL = 0.
5. Since VSUBTOG and VSUBPOL are VD synchronous type
6. VSUB will be asserted low after three HD cycles.
registers, the falling edge of VD will update the serial writes
from Step 1 here.
registers, the falling edge of VD will update the serial writes
from Step 4 here.
4
5
3 LINES
6
AD9898