AD9898KCP-20 Analog Devices Inc, AD9898KCP-20 Datasheet - Page 46

• Manufacturer Part Number: AD9898KCP-20
• Description: IC CCD SIGNAL PROC/GEN 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9898KCP-20

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 3
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9898
POWER-UP
Recommended Power-Up Sequence for Master Mode
When the AD9898 is powered up, the following sequence is
recommended. (Refer to Figure 51 for each step.)
1. Turn on power supplies for AD9898.
2. Apply the CLI master clock input. CLI will be output on
3. Reset the internal AD9898 registers. Write a 0x000000 to
4. Program the DIGSTBY and AFESTBY registers
OUTCONT
(INTERNAL
(OUTPUT)
(OUTPUT)
OUTPUTS
(OUTPUT)
(OUTPUT)
DIGITAL
WRITES
DCLK2
(INPUT)
SIGNAL)
DCLK2 (Pin 16) at this time.
the SW_RESET register (Addr 0x00). This will set all
internal register values to their default values. (This step is
optional because an internal power-on reset circuit is
applied at power-up.)
(Addr 0x05) = 1, and program all other necessary control
registers.
(INPUT)
SERIAL
DCLK1
VDD
CLI
VD
HD
2
1
NOTES
1
2
3
4
OUTCONT IS AN INTERNAL SIGNAL CONTROLLED USING REGISTER OUTCONT_REG (ADDR 0x05).
DCLK2 WILL BE OUTPUT ON FD/DLCK2, PIN 16, PROVIDING REGISTER DCLK2SEL (ADDR 0xD5) = 1.
IT TAKES 11 CLI CLOCKS FROM WHEN OUTCONT GOES HIGH UNTIL VD, HD, AND DIGITAL OUTPUT DATA IS VALID.
THERE IS 500 s SETTLING TIME FROM WHEN THE DIGSTBY REGISTER IS SET TO WHEN THE DLCK1 IS STABLE.
1
2
Figure 51. Recommended Power-Up Sequence and Synchronization, Master Mode
t
PWR
H1, V1, V2, V3, VSG1, VSG2, VSUB, SUBCK, FD
H2, RG, MSHUT, STROBE
4
t
SETTLING
5
4
6
7
8
9
t
DELAY
–46–
3
1H
ODD FIELD
10. Program control register MODE (Addr 0x0A) = 1. This
5. Program system registers (Addr 0x14).
6. Program Mode_A registers (Addr 0x15).
7. Program Mode_B registers (Addr 0x16).
8. Program OUTCONT_REG register (addr 0x05) = 1.
9. Program control register MODE (Addr 0x0A) = 0. This
(The internal OUTCONT signal will be asserted high at
this time and will enable the digital outputs.)
selects Mode_A operation. (This step is optional because
the AD9898 defaults to Mode_A at initial power-up.)
selects Mode_B operation. Complete this write at least
four CLI cycles before start of the next field.
1V
10
EVEN FIELD
ODD FIELD
REV. 0