AD9898KCP-20 Analog Devices Inc, AD9898KCP-20 Datasheet - Page 44

• Manufacturer Part Number: AD9898KCP-20
• Description: IC CCD SIGNAL PROC/GEN 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9898KCP-20

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 3
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9898
STROBE Control
The AD9898 provides a STROBE output pulse that can be used
to trigger the camera flash circuit. STROBE operation is set by
only one register, as described in Table XXV. The STROBE
output is held Low when STROBE_EN (Addr 0x0B) is set to
0 and enabled when set to 1. Providing STROBE_EN = 1, the
STROBE output pulse will be asserted High on the rising edge of
the last SUBCK pulse in the field, as shown in Figure 48.
Figure 48 also shows the STROBE pulse asserted Low again on
the rising edge of VSG.
SLAVE AND MASTER MODE OPERATION
The AD9898 can be operated in either slave mode or master
mode. It defaults to the slave mode operation at power-up. The
(PIXEL COUNTER)
H-GRAY CODE
Figure 49. External VD/HD and Internal 12-Bit H-Gray Code Counter Synchronization, SLAVE Mode
STROBE
SUBCK
VSG1–
VSG2
COUNTER
VD
CLI
1. STROBE OUTPUT ASSERTED HIGH ON RISING EDGE OF LAST SUBCK PULSE.
2. STROBE OUTPUT ASSERTED LOW ON NEGATIVE EDGE OF VSG PULSE.
VD
HD
INTERNAL 12-BIT H-GRAY CODE COUNTER IS RESET 7 CLOCK CYCLES AFTER THE HD FALLING EDGE.
X
SET STROBE_EN (ADDR 0x0B) = 1
X
X
3ns MIN
X
X
X
X
Figure 48. STROBE Output Timing
X
H-COUNTER
RESET
X
0
1
1
2
–44–
3
SLAVE_MODE register (Addr 0xD6) can be used to configure
the AD9898 into master mode by setting SLAVE_MODE = 0.
Slave Mode Operation
While operating in slave mode, VD, HD, and VGATE are pro-
vided externally from the image processor. VGATE is input
active high on Pin 45. Unlike master mode operation, there is a
7 CLI clock cycle delay from the falling edge of HD to when the
12-bit gray code H counter is reset to zero (see Figure 49).
Master Mode Operation
While operating in master mode, VD and HD are outputs and
the SYNC/VGATE pin is configured as an external SYNC input.
Master mode is selected by setting register SLAVE_MODE
(Addr 0xD6) = 0.
4
5
6
7
8
t
EXP
9
10 11
12
13 14
H-COUNTER
RESET
0
2
1
2
3
4
REV. 0