MAX9257GTL/V+ Maxim Integrated Products, MAX9257GTL/V+ Datasheet - Page 10

• Manufacturer Part Number: MAX9257GTL/V+
• Description: IC SER/DESER PROG 40TQFN-EP
• Manufacturer: Maxim Integrated Products

Specifications of MAX9257GTL/V+

• Function: Serializer/Deserializer
• Data Rate: 840Mbps
• Input Type: Serial
• Output Type: LVDS
• Number Of Inputs: 16
• Number Of Outputs: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Fully Programmable Serializer/Deserializer
with UART/I
10
TQFN
19, 34
20, 33
2, 11,
1, 18
3–8
10
12
13
14
15
16
17
21
22
23
24
25
26
27
28
9
______________________________________________________________________________________
PIN
22, 41
23, 40
LQFP
3, 14,
2, 21
4–9
10
11
15
16
17
18
19
20
26
27
28
29
30
31
32
33
DIN15/GPIO7
HSYNC_IN
VSYNC_IN
DIN[9:14]/
GPIO[1:6]
GND
GND
GND
PCLK_IN
V
V
V
SDA/RX
SCL/TX
NAME
GPIO8
GPIO9
V
CCLVDS
CCSPLL
SDO+
CCFPLL
SDO-
GND
V
CCIO
CC
LVDS
FPLL
SPLL
2
C Control Channel
Single-Ended Input/Output Buffer Supply Voltage. Bypass V
0.001µF capacitors in parallel as close as possible to the device with the smallest value
capacitor closest to V
Digital Supply Ground
Data Input/General Purpose Input/Output. When a serial-data word is less than 18 bits
word length, DIN_ not programmed as data inputs becomes GPIO (Table 22). DIN[9:14]
are internally pulled down to ground.
Filter PLL Ground
Filter PLL Supply Voltage. Bypass V
in parallel as close as possible to the device with the smallest value capacitor closest to
V
Data Input/General Purpose Input/Output. When a serial-data word is less than 18 bits
word length, DIN_ not programmed as data input becomes GPIO (Table 22). DIN15 is
internally pulled down to ground.
Horizontal SYNC Input. HSYNC_IN is internally pulled down to ground.
Vertical SYNC Input. VSYNC_IN is internally pulled down to ground.
Parallel Clock Input. PCLK_IN latches data and sync inputs and provides the PLL reference
clock. PCLK_IN is internally pulled down to ground.
O p en- D r ai n C ontr ol C hannel Outp ut. S C L/TX b ecom es S C L outp ut w hen U ART- to- I
acti ve. S C L/TX b ecom es TX outp ut w hen U ART- to- I
Open-Drain Control Channel Input/Output. SDA/RX becomes bidirectional SDA when
UART-to-I
output requires a pullup to V
Digital Supply Voltage. Bypass V
as cl ose as p ossi b l e to the d evi ce w i th the sm al l est val ue cap aci tor cl osest to V
General Purpose Input/Output
General Purpose Input/Output
Spread PLL Supply Voltage. Bypass V
capacitors in parallel as close as possible to the device with the smallest value capacitor
closest to V
SPLL Ground
LVDS Ground
Serial LVDS Inverting Output
Serial LVDS Noninverting Output
LVDS Supply Voltage. Bypass V
parallel as close as possible to the device with the smallest value capacitor closest to
V
CCFPLL
CCLVDS
.
.
2
C is active. SDA/RX becomes RX input when UART-to-I
CCSPLL
.
CCIO
.
CC
.
CCLVDS
CC
CCFPLL
to ground with 0.1µF and 0.001µF capacitors in p ar al l el
CCSPLL
FUNCTION
to GND
to GND
MAX9257 Pin Description
to GND
LVDS
2
C i s b yp assed . E xter nal l y p ul l up to V
FPLL
with 0.1µF and 0.001µF capacitors in
SPLL
with 0.1µF and 0.001µF capacitors
with 0.1µF and 0.001µF
CCIO
to GND with 0.1µF and
2
C is bypassed. SDA
C C
.
2
C i s
C C
.