MAX9257GTL/V+ Maxim Integrated Products, MAX9257GTL/V+ Datasheet - Page 40

• Manufacturer Part Number: MAX9257GTL/V+
• Description: IC SER/DESER PROG 40TQFN-EP
• Manufacturer: Maxim Integrated Products

Specifications of MAX9257GTL/V+

• Function: Serializer/Deserializer
• Data Rate: 840Mbps
• Input Type: Serial
• Output Type: LVDS
• Number Of Inputs: 16
• Number Of Outputs: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Fully Programmable Serializer/Deserializer
with UART/I
I
to data and clock lines. There are tradeoffs between
power dissipation and speed, and a compromise must
be made in choosing pullup resistor values. Every device
connected to the bus introduces some capacitance even
when device is not in operation. I
40
2
C requires pullup resistors to provide a logic-high level
ADDRESS
______________________________________________________________________________________
0
1
2
Control channel start timeout: (STO) times out if ECU does not start using control channel within this amount of time
after control channel session is enabled.
BITS
7:6
5:4
2:0
7:5
4:0
7:4
3:0
Choosing I
3
DEFAULT
11111
1010
0000
101
000
10
11
0
2
2
C Control Channel
C Pullup Resistors
2
C specifies 300ns rise
STOCNT
SPREAD
PWIDTH
STODIV
PAREN
PRATE
SRATE
NAME
Pixel clock frequency range
00 = 5MHz to 10MHz
01 = 10MHz to 20MHz
10 = 20MHz to 40MHz (default)
11 = 40MHz to 70MHz
Serial-data rate range
00 = 60Mbps to 100Mbps
01 = 100Mbps to 200Mbps
10 = 200Mbps to 400Mbps
11 = 400Mbps to 840Mbps (default)
Parity enable
Parallel data width
(includes HSYNC and VSYNC, excludes DCB, INV, and parity bits)
000 = 10
001 = 12
010 = 14
011 = 16
Spread-spectrum setting
For PRATE ranges 00, 01: all spread options possible
For PRATE ranges 10, 11: maximum spread is 2%
000 = Off (default)
001 = 1.5%
010 = 1.75%
011 = 2%
Reserved (set to 11111)
Control channel start timeout divider
Pixel clock is first divided by:
0000 = 16
0001 = 16
0010 = 16
0011 = 16
0100 = 16
0101 = 32
0110 = 64
0111 = 128
Control channel start timeout counter
Divided pixel clock is used to count up to (STOCNT + 1)
times to go from low to high (30% to 70%) for fast mode,
which is defined for a date rate up to 400kbps (see I
specifications for details). To meet the rise time require-
ment, choose the pullup resistors so the rise time
t
becomes too slow, the setup and hold times may not be
met and waveforms will not be recognized.
R
= 0.85R
PULLUP
1000 = 256
1001 = 512
1010 = 1024 (default)
1011 = 2048
1100 = 4096
1101 = 8192
1110 = 16,384
1111 = 32,768
DESCRIPTION
x C
0 = disabled (default), 1 = enabled
100 = 18
101 = 18 (default)
110 = 18
111 = 18
100 = Off
101 = 3%
110 = 3.5%
111 = 4%
BUS
MAX9257 Register Table
< 300ns. If the transition time
2
C