MAX9257GTL/V+ Maxim Integrated Products, MAX9257GTL/V+ Datasheet - Page 31

• Manufacturer Part Number: MAX9257GTL/V+
• Description: IC SER/DESER PROG 40TQFN-EP
• Manufacturer: Maxim Integrated Products

Specifications of MAX9257GTL/V+

• Function: Serializer/Deserializer
• Data Rate: 840Mbps
• Input Type: Serial
• Output Type: LVDS
• Number Of Inputs: 16
• Number Of Outputs: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Assuming a UART bit rate of 2Mbps, REG2[7:4],
REG3[7:4] = 100 (Table 26), CTO = 64, CTO timeout
calculated as:
The MAX9258 powers up when the power-down input
PD goes high. After approximately 130µs, CCEN goes
high, indicating the control channel is available. This
delay is required because the analog circuitry has to
fully wake up. There are two ways to power up the
MAX9257. The MAX9257 powers up according to the
state of REM. ECU powers up MAX9257 remotely (ECU
sends command to power up) when REM is pulled to
V
voltage when REM is grounded.
When REM is grounded, the MAX9257 fully powers up
when power is applied. The power-down bit PD
(REG4[4]) is disabled and serialization bit SEREN
(REG4[3]) is enabled. If PCLK_IN is not running, the
MAX9257 stays in the control channel. After PCLK_IN is
applied, the control channel times out due to STO, ETO,
or EF. The MAX9257 starts the handshaking after the
MAX9257 locks to PCLK after 32,768 clock cycles. If
PCLK_IN is running, serialization starts automatically
after PLL of the MAX9257 locks to PCLK_IN with default
values in the registers.
When REM is pulled up to V
in a low power state, drawing less than 100µA supply
current. To wake-up the MAX9257, the ECU first trans-
mits a dummy frame 0xDB and then waits at least
100µs to allow the MAX9257’s internal analog circuitry
to fully power up. Then the ECU configures the
MAX9257 registers, including a write to disable the PD
bit (REG4[4]) so that the MAX9257 does not return
back to the low power state. Every packet needs to
start with a synchronization frame (see the UART sec-
tion). If the PD bit is not disabled within 70ms after
transmitting the dummy frame, the MAX9257 returns to
the low power state and the whole power-up sequence
needs to be repeated. After configuration is complete,
the ECU also needs to enable the SEREN bit to start the
video phase.
At initial power-up with REM pulled to V
of SEREN bit is 0, so STO and ETO timers are not active.
Control channel is enabled as long as SEREN is 0.
This allows the control channel to be used for extensive
CC
Powering the MAX9257 with Serialization Enabled
. The MAX9257 powers up according to the supply
Fully Programmable Serializer/Deserializer
t
CTO
______________________________________________________________________________________
Remote Power-Up of the MAX9257
= (0.5µs) × 64 = 32µs
(REM = Ground at Power-Up)
CC
(REM = Pulled Up to V
, the MAX9257 wakes up
Link Power-Up
CC
with UART/I
, default value
CC
)
programming at initial power-up without the channel
timing out. UART, parity, framing and packet errors in
the control channel communications are reported if end
frame is used to close control channel (see the
MAX9258 Error Checking and Reporting section). For
faster identification of errors, verify every write com-
mand by reading back the registers before enabling
serialization.
When the control channel is open, the ECU writes to the
PD bit to power down the MAX9257. In this case, to
power up the MAX9257 again, the power-up sequence
explained in the Remote Power-Up of the MAX9257 (REM
= Pulled Up to V
MAX9258 has a PD input that powers down the device.
The MAX9258 has an open-drain ERROR output. This
output indicates various error conditions encountered
during the operation of the system. When an error con-
dition is detected and needs to be reported, ERROR
asserts low. ERROR indicates three error conditions:
UART, video parity, and PRBS errors.
During control channel communication in base mode,
the MAX9257/MAX9258 record UART frame, parity, and
packet errors. I
MAX9257 when I
the control channel by using end frame (EF), the
MAX9257 sends a special internal UART frame back to
the MAX9258 called error frame. The MAX9257 UART
and I
MAX9258 receives the error frame and records the
error status in its UART error register (REG13). ECU
must use end frame to the close control channel for the
MAX9257 to report back UART and I
MAX9258. Whenever one of the bits in the UART error
register is 1, ERROR asserts low. The UART error regis-
ter is reset when ECU reads it, and ERROR deasserts
high immediately if UART errors were the only reason
that ERROR was asserted low. If the MAX9258 is not
locked (LOCK = low), UART error is not reported.
When video parity check is enabled (REG0[3] in both
devices), the MAX9258 counts the number of video pari-
ty errors by checking recovered video words. Value of
this counter is reflected in PAERRHI (8 MSB bits,
REG11) and PAERRLO (8 LSB bits, REG10). If the num-
ber of detected parity errors is greater than or equal to
the parity error threshold PATHRHI (REG9) and
PATHRLO (REG8), then ERROR asserts low. In this
MAX9258 Error Checking and Reporting
2
C errors are reset at the next control channel. The
2
C Control Channel
CC
2
C interface is enabled. If ECU closes
2
) section needs to be repeated. The
C errors are also recorded by
Link Power-Down
Video Parity Errors
2
C errors to the
UART Errors
31