FIN24ACMLX Fairchild Semiconductor, FIN24ACMLX Datasheet

Page 1

... PDA, video camera, automotive Ordering Information Package Order Number Number FIN24ACGFX BGA042 FIN24ACMLX MLP040 Pb-Free package per JEDEC J-STD-020B. BGA and MLP packages available in tape and reel only. µSerDes is a trademark of Fairchild Semiconductor Corporation. TM © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 General Description The FIN24AC µ ...

Page 2

... Functional Block Diagram CKREF STROBE DP[21:22] DP[1:20] DP[23:24] CKP S1 S2 DIRI © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 Word PLL 0 Boundary Generator I cksint Serializer Control Serializer oe Deserializer Deserializer cksint Control WORD CK Generator Control Logic DIRO Freq. Direction Control Control oe Power Down Control Figure 1 ...

Page 3

... The DSO/DSI serial port terminals have been arranged such that when one device is rotated 180° to the other device, the serial connections properly align without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross. © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 Number of ...

Page 4

... Connection Diagrams DP[10] DP[11] DP[12] DP[13] DP[14] DP[15] DP[16] Figure 2. Terminal Assignments for MLP (Top View (Top View) © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 DP[ DDP CKP Pin Assignments DP[9] DP[7] DP[5] B DP[11] DP[10] DP[6] C CKP DP[12] DP[8] D DP[13] DP[14] ...

Page 5

... Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 Turn-Around Functionality The device passes and inverts the DIRI signal through the device asynchronously to the DIRO signal. Care must be taken during design to ensure that no contention occurs between the deserializer outputs and the other devices on this port ...

Page 6

... CKS0 No Data Figure 5. Serializer Timing Diagram (CKREF does not equal STROBE) © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 The Phase-Locked Loop (PLL) must receive a stable CKREF signal to achieve lock prior to any valid data being sent. The CKREF signal can be used as the data STROBE signal, provided that data can be ignored during the PLL lock phase ...

Page 7

... CKS0 No Data Figure 6. Serializer Timing Diagram Using Provided Bit Clock (No CKREF) © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 (Continued) A third method of serialization can be accomplished with a free running bit clock on the CKSI signal. This mode is enabled by grounding the CKREF signal and driving the DIRI signal HIGH ...

Page 8

... DP[1:24] WORD n-2 Figure 8. Deserializer Timing Diagram (Serializer Source: CKREF does not equal STROBE) © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 When the DIRI signal is asserted LOW, the device is configured as a deserializer. Data is captured on the serial port and deserialized through use of the bit clock sent with the data ...

Page 9

... Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 resistor FIN24AC device is configured as an unidi- rectional serializer, unused data I/O can be treated as unused inputs. If the FIN24AC is hardwired as a deseri- alizer, unused data I/O can be treated as unused out- puts ...

Page 10

... The output of the PLL is a bit clock that is used to serialize the data. The bit clock is also sent source syn- chronously with the serial data stream. © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 There are two ways to disable the PLL: by entering the ...

Page 11

... Generates an embedded word clock for each strobe signal. REFCK CNTL[0:1] Sending Unit DATA [0:19 Note: Data on serializer pins DP[21:22] is output on pins DP[23:24] of the deserializer. Figure 12. Unidirectional Serializer and Deserializer © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 Unidirectional Data Transfer BIT PLL Gen. – – Serializer CKSO ...

Page 12

... Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom. ■ Do not place test points on differential serial wires. ■ Use differential serial wires a minimum of 2cm away from the antenna. © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 FIN24AC FIN24AC CKREF ...

Page 13

... Symbol Supply Voltage DDA DDS V Supply Voltage DDP T Operating Temperature A V Supply Noise Voltage DDA-PP © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 Parameter All Pins CKSO, CKSI, DSO to GND Parameter 13 Min. Max. Unit -0.5 +4.6 V -0.5 +4.6 V ...

Page 14

... Voltage is referenced to GROUND unless otherwise specified (except ΔV and the difference in device ground levels between the CTL driver and the CTL receiver. GO © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 Test Conditions V = 3.3 ± 0.3 DDP I = –2 2.5 ± ...

Page 15

... CPWL t LVCMOS Input Transition CLKT Time t STROBE Pulse Width SPWH HIGH/LOW © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 Test Conditions All DP and Control Inputs CKREF DIR = 1 All DP and Control Inputs CKREF DIR = 0 All DP and Control Inputs CKREF DIR = 1 All DP and Control Inputs ...

Page 16

... If the CKREF is not equal to STROBE for the serializer, the CKP signal does not maintain a 50% duty cycle. The low time of CKP remains 13 bit times. © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 Test Conditions ...

Page 17

... Capacitance of Input Only Signals, IN CKREF, STROBE, S1, S2, DIRI C Capacitance of Parallel Port Pins Capacitance of Differential I/O Signals IO-DIFF © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 Test Conditions DIRI LOW-to-HIGH or HIGH-to-LOW DIRI LOW-to-HIGH DIRI HIGH-to-LOW DIRI = 0, S1( and S2(1) = LOW-to-HIGH, Figure 29 (9) ...

Page 18

... Maximum power is measured at the maximum V Typical values are measured 2.5V TLH 80% V 20% DIFF V = (DS+) – (DS-) DIFF DS – DS- Figure 17. CTL Output Load and Transition Times © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 DS+ DUT DS- Figure 15. CTL Input Common Mode Test Circuit T 999h b ...

Page 19

... Figure 21. Deserializer Data Valid Window Time and Clock Output Parameters t TCCD STROBE V DD/2 CKS0 DIFF CKS0+ Note: STROBE = CKREF Figure 23. Serializer Clock Propagation Delay © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 (Continued) Data t HTC CKREF t PDV 50% RCOL Note: CKREF signal is free running. ...

Page 20

... Figure 27. PLL Loss of Clock Disable Time t PLZ(HZ DS+,CKS0+ HIGH-Z DS-,CKS0- Note: CKREF must be active and PLL must be stable. Figure 29. Serializer Enable and Disable Time © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 (Continued) CKSO- t H_DS CKSO+ DSO+ DSO- Note: Data is typically edge aligned with the clock. ...

Page 21

... EIA/JEDEC RS-481 rotational and 10° maximum component rotation Sketch A (Side or Front Sectional View) Component Rotation Shipping Reel Dimension Dia A max Tape Dia A Dim B Width Max. Min. 8 330 1.5 12 330 1.5 16 330 1.5 © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0 Min. ±0.1 ±0.1 ± ...

Page 22

... A, B, and C). 10° maximum component rotation Sketch A (Side or Front Sectional View) Component Rotation Shipping Reel Dimension Dia A max Tape Dia A Dim B Width Max. Min. 8 330 1.5 12 330 1.5 16 330 1.5 © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 (Continued Min. ±0.1 ± ...

Page 23

... A1 CORNER INDEX AREA (QA CONTROL VALUE) 1.00 MAX 0. SEATING PLANE Figure 31. Pb-Free, 42-Ball, Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 3.50 2X 0.10 C (0.6) 4.50 0.5 0.89±0.082 0.45±0.05 0.21± ...

Page 24

... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 32. Pb-Free, 40-Terminal, Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square © 2005 Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 (DATUM A) 24 www.fairchildsemi.com ...

Page 25

... Fairchild Semiconductor Corporation FIN24AC Rev. 1.0.3 25 www.fairchildsemi.com ...