FIN24ACMLX Fairchild Semiconductor, FIN24ACMLX Datasheet - Page 6

• Manufacturer Part Number: FIN24ACMLX
• Description: IC SERIALIZER/DESERIALZR 40MLP
• Manufacturer: Fairchild Semiconductor
• Series: SerDes™r

Specifications of FIN24ACMLX

• Function: Serializer/Deserializer
• Data Rate: 520Mbps
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 20
• Number Of Outputs: 20
• Voltage - Supply: 1.65 V ~ 3.6 V
• Operating Temperature: -30°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-MLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
Serializer Operation: (Figure 4)
Serializer Operation: (Figure 5),
Serializer Operation Mode
The serializer configurations are described in the following sections. The basic serialization circuitry works essentially
the same in these modes, but the actual data and clock streams differ depending on if CKREF is the same as the
STROBE signal or not. When the CKREF equals STROBE, the CKREF and STROBE signals have an identical fre-
quency of operation, but may or may not be phase aligned. When CKREF does not equal STROBE, each signal is dis-
tinct and CKREF must be running at a frequency high enough to avoid any loss of data condition. CKREF must never
be a lower frequency than STROBE.
MODE 1, 2, or 3
DIRI = 1,
CKREF = STROBE
DIRI = 1,
CKREF does not = STROBE
STROBE
DP[1:24]
CKREF
DPI[1:24]
CKS0
CKREF
DSO
CKS0
DSO
WORD n-1
b 24 b 25 b 26
WORD n-1
No Data
WORD n-2
Figure 5. Serializer Timing Diagram (CKREF does not equal STROBE)
Figure 4. Serializer Timing Diagram (CKREF equals STROBE)
b 1 b 2 b 3
b 1
The Phase-Locked Loop (PLL) must receive a stable CKREF signal to achieve
lock prior to any valid data being sent. The CKREF signal can be used as the data
STROBE signal, provided that data can be ignored during the PLL lock phase.
Once the PLL is stable and locked, the device can begin to capture and serialize
data. Data is captured on the rising edge of the STROBE signal and serialized.
The serialized data stream is synchronized and sent source synchronously with a
bit clock with an embedded word boundary. When in this mode, the internal dese-
rializer circuitry is disabled; including the serial clock, serial data input buffers, the
bi-directional parallel outputs, and the CKP word clock. The CKP word clock is
driven HIGH.
If the same signal is not used for CKREF and STROBE, the CKREF signal must
be run at a higher frequency than the STROBE rate to serialize the data correctly.
The actual serial transfer rate remains at 26 times the CKREF frequency. A data
bit value of zero is sent when no valid data is present in the serial bit stream. The
operation of the serializer otherwise remains the same.
The exact frequency that the reference clock needs is dependent upon the stabil-
ity of the CKREF and STROBE signal. If the source of the CKREF signal imple-
ments spread spectrum technology, the maximum frequency of this spread
spectrum clock should be used in calculating the ratio of STROBE frequency to
the CKREF frequency. Similarly if the STROBE signal has significant cycle-to-
cycle variation, the maximum cycle-to-cycle time needs to be factored into the
selection of the CKREF frequency.
b 2
b 4 b 5 b 6 b 7
b 3
b 4
WORD n-1
WORD n
6
WORD n
WORD n-1
b 22 b 23 b 24 b 25 b 26
b 22 b 23 b 24 b 25 b 26
No Data
b 1
b 2
WORD n+1
WORD n+1
b 3
b 1 b 2 b 3
WORD n
WORD n
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b 4
b 5