CYV15G0204RB-BGC Cypress Semiconductor Corp, CYV15G0204RB-BGC Datasheet - Page 9

• Manufacturer Part Number: CYV15G0204RB-BGC
• Description: IC DESERIAL HOTLINK 256LBGA
• Manufacturer: Cypress Semiconductor Corp
• Type: Deserializerr

Specifications of CYV15G0204RB-BGC

• Package / Case: 256-LBGA Exposed Pad, 32-HLBGA
• Function: Deserializer
• Data Rate: 1.485Gbps
• Input Type: PECL
• Output Type: LVTTL
• Number Of Inputs: 2
• Number Of Outputs: 2
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Operating Supply Voltage: 3.3 V
• Supply Current: 700 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 38-02103 Rev. *C
Pin Definitions
CYV15G0204RB Dual HOTLink II Deserializing Reclocker
DATA[6:0]
RXRATE[A..B]
SDASEL[2..1][A..B]
[1:0]
RXPLLPD[A..B]
RXBIST[A..B][1:0]
ROE2[A..B]
ROE1[A..B]
Factory Test Modes
SCANEN2
TMEN3
ROUTA1±
ROUTB1±
ROUTA2±
ROUTB2±
INA1±
INB1±
INA2±
INB2±
TMS
TCLK
TDO
TDI
TRST
Note
4. See
Name
Internal Device Configuration Latches
Analog I/O
JTAG Interface
“Device Configuration and Control Interface” on page 12
(continued)
Internal Latch
Internal Latch
LVTTL input
asynchronous,
internal pull-up
Internal Latch
Internal Latch
Internal Latch
Internal Latch
LVTTL input,
internal pull-down
LVTTL input,
internal pull-down
CML Differential
Output
CML Differential
Output
Differential Input
Differential Input
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-down
3-State LVTTL
Output
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-up
I/O Characteristics Signal Description
[4]
[4]
[4]
[4]
[4]
[4]
Control Data Bus. The DATA[6:0] bus is the input data bus used to configure the
device. The WREN input writes the values of the DATA[6:0] bus into the latch
specified by address location on the ADDR[2:0] bus.
configuration latches within the device, and the initialization value of the latches upon
the assertion of RESET.
the device.
Receive Clock Rate Select.
Signal Detect Amplitude Select.
Receive Channel Power Control.
Receive Bist Disabled.
Reclocker Differential Serial Output Driver 2 Enable.
Reclocker Differential Serial Output Driver 1 Enable.
Factory Test 2. SCANEN2 input is for factory testing only. This input may be left as
a NO CONNECT, or GND only.
Factory Test 3. TMEN3 input is for factory testing only. This input may be left as a
NO CONNECT, or GND only.
Primary Differential Serial Data Output. The ROUTx1± PECL-compatible CML
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC-coupled for
PECL-compatible connections.
Secondary Differential Serial Data Output. The ROUTx2± PECL-compatible CML
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible
connections.
Primary Differential Serial Data Input. The INx1± input accepts the serial data
stream for deserialization. The INx1± serial stream is passed to the receive CDR
circuit to extract the data content when INSELx = HIGH.
Secondary Differential Serial Data Input. The INx2± input accepts the serial data
stream for deserialization. The INx2± serial stream is passed to the receiver CDR
circuit to extract the data content when INSELx = LOW.
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained
high for ≥5 TCLK cycles, the JTAG test controller is reset.
JTAG Test Clock.
Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not
selected.
Test Data In. JTAG data input port.
JTAG reset signal. When asserted (LOW), this input asynchronously resets the
JTAG test access port controller.
for detailed information on the internal latches.
Table 4 on page 14
shows how the latches are mapped in
[3]
CYV15G0204RB
Table 3 on page 13
Page 9 of 24
lists the
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