DS15MB200TSQX/NOPB National Semiconductor, DS15MB200TSQX/NOPB Datasheet - Page 6

• Manufacturer Part Number: DS15MB200TSQX/NOPB
• Description: IC MUX/BUFFER DUAL 1.5GBPS 48LLP
• Manufacturer: National Semiconductor
• Type: MUXr

Specifications of DS15MB200TSQX/NOPB

• Tx/rx Type: LVDS
• Delay Time: 1.0ns
• Capacitance - Input: 2pF
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 275mA
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS15MB200TSQX

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SUPPLY CURRENT (Static)
I
I
SWITCHING CHARACTERISTICS — LVDS OUTPUTS
t
t
t
t
t
t
t
t
t
t
CC
CCZ
LHT
HLT
PLHD
PHLD
SKD1
SKCC
JIT
ON
ON2
OFF
Symbol
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified.
Note 8: Typical parameters are measured at V
Note 9: Differential output voltage V
Note 10: Output offset voltage V
Note 11: Jitter is not production tested, but guaranteed through characterization on a sample basis.
Note 12: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = V
750MHz, t
Note 13: Deterministic Jitter, or D
voltage = V
Note 14: Total Jitter, or T
= V
Note 15: Not production tested. Guaranteed by statistical analysis on a sample basis at the time of characterization.
ID
= 500mV, 2
r
Supply Current
Supply Current - Powerdown
Mode
Differential Low to High Transition
Time
Differential High to Low Transition
Time
Differential Low to High
Propagation Delay
Differential High to Low
Propagation Delay
Pulse Skew
Output Channel to Channel Skew
Jitter (0% Pre-emphasis)
(Note 11)
LVDS Output Enable Time
LVDS Output Enable Time from
Powerdown Mode
LVDS Output Disable Time
ID
= t
= 500mV, K28.5 pattern at 1.5 Gbps, t
f
= 50ps (20% to 80%).
7-1
PRBS pattern at 1.5 Gbps, t
J
, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter have been subtracted. The input voltage
Parameter
OS
J
, is measured to a histogram mean with a sample size of 350 hits. Stimulus and fixture jitter have been subtracted. The input
OD
is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
is defined as ABS(OUT+–OUT−). Differential input voltage V
DD
r
= 3.3V, T
= t
r
f
= t
= 50ps (20% to 80%).
(Continued)
f
All inputs and outputs enabled and
active, terminated with external load of
100Ω between OUT+ and OUT-.
ENA_0 = ENB_0 = ENL_0 = ENA_1 =
ENB_1 = ENL_1 = L
Use an alternating 1 and 0 pattern at
200 Mb/s, measure between 20% and
80% of V
Use an alternating 1 and 0 pattern at
200 Mb/s, measure at 50% V
between input to output.
|t
Difference in propagation delay (t
or t
(Note 15)
RJ - Alternating 1 and 0 at 750MHz
(Note 12)
DJ - K28.5 Pattern, 1.5 Gbps (Note 13)
TJ - PRBS 2
14)
Time from ENA_n, ENB_n, or ENL_n to
OUT
active.
Time from ENA_n, ENB_n, or ENL_n to
OUT
to active.
Time from ENA_n, ENB_n, or ENL_n to
OUT
TRI-STATE or Powerdown mode.
= 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
PLHD
A
PHLD
= 25˚C. They are for reference purposes, and are not production-tested.
±
±
±
–t
change from TRI-STATE to
change from Powerdown Mode
change from active to
PHLD
) among all output channels.
OD
. (Note 15)
| (Note 15)
7
-1 Pattern, 1.5 Gbps (Note
Conditions
6
OD
PLHD
ID
is defined as ABS(IN+–IN−).
Min
(Note 8)
Typ
225
170
170
0.6
1.0
1.0
1.1
0.5
25
50
20
14
10
ID
= 500mV, 50% duty cycle at
Max
275
250
250
115
4.0
2.5
2.5
1.5
1.5
75
34
28
20
12
psrms
Units
psp-p
psp-p
mA
ps
ps
ns
ns
ps
ps
µs
µs
ns