PCA9541APW/01,112 NXP Semiconductors, PCA9541APW/01,112 Datasheet - Page 11

• Manufacturer Part Number: PCA9541APW/01,112
• Description: IC I2C 2:1 SELECTOR 16-TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9541APW/01,112

• Package / Case: 16-TSSOP
• Applications: 2-Channel I²C Multiplexer
• Interface: I²C, SMBus
• Voltage - Supply: 2.3 V ~ 5.5 V
• Mounting Type: Surface Mount
• Maximum Operating Frequency: 400 KHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4938-5; 935289365112

NXP Semiconductors
Table 6.
Legend: * default value
[1]
Table 7.
Table 8.
Legend: * default value
[1]
PCA9541A_3
Product data sheet
Bit
1
0
Bit
7
6
5
4
3
2
1
0
NTESTON
Default values are the same for PCA9541A/01, PCA9541A/03.
Default values are the same for PCA9541A/01, PCA9541A/03.
7
Symbol
BUSINITMSK
INTINMSK
Symbol
NTESTON
TESTON
-
BUSINIT
NBUSON
BUSON
NMYBUS
MYBUS
Register 0 - Interrupt Enable (IE) register bit description
Register 1 - Control Register (B1:B0 = 01b) bit allocation
Register 1 - Control Register (B1:B0 = 01b) bit description
8.3.2 Register 1: Control Register (B1:B0 = 01b)
TESTON
6
Access Value
R/W
R/W
R only
R/W
R only
R/W
R only
R/W
The Control Register described below is identical for both the masters. Nevertheless,
there are physically 2 internal Control Registers, one for each upstream channel. When
master 0 reads/writes in this register, the internal Control Register 0 will be accessed.
When master 1 reads/writes in this register, the internal Control Register 1 will be
accessed.
Access Value
R/W
R/W
0*
1
0*
1
0*
0*
1
see
Table 11
see
Table 11
see
Table 11
see
Table 11
0*
1
0*
1
5
0
[1]
[1]
Description
After connection is requested and Bus Initialization requested (BUSINIT = 1),
an interrupt on INT will be generated when the bus initialization is done.
Remark: Channel switching is done after bus initialization completed.
After connection is requested and Bus Initialization requested (BUSINIT = 1),
an interrupt on INT will not be generated when the bus initialization is done
(masked).
Remark: Channel switching is done after bus initialization completed.
Interrupt on INT_IN will generate an interrupt on INT.
Interrupt on INT_IN will not generate an interrupt on INT (masked)
Description
A logic level HIGH to the INT line of the other channel is sent (interrupt
cleared).
A logic level LOW to the INT line of the other channel is sent (interrupt
generated).
A logic level HIGH to the INT line is sent (interrupt cleared).
A logic level LOW to the INT line is sent (interrupt generated).
not used
Bus initialization is not requested.
Bus initialization is requested.
NBUSON bit along with BUSON bit decides whether any upstream channel
is connected to the downstream channel or not. See
Table
BUSON bit along with the NBUSON bit decides whether any upstream
channel is connected to the downstream channel or not. See
Table
NMYBUS bit along with MYBUS bit decides which upstream channel is
connected to the downstream channel. See
MYBUS bit along with the NMYBUS bit decides which upstream channel is
connected to the downstream channel. See
BUSINIT
Rev. 03 — 16 July 2009
12.
11, and
2-to-1 I
4
Table
2
C-bus master selector with interrupt logic and reset
NBUSON
12.
3
…continued
BUSON
2
Table
Table
NMYBUS
9,
9,
PCA9541A
Table
Table
Table
1
© NXP B.V. 2009. All rights reserved.
11, and
11, and
10,
Table
Table
MYBUS
Table
Table
10,
11, and
0
11 of 41
12.
12.