PI7C9X7952AFDE Pericom Semiconductor, PI7C9X7952AFDE Datasheet - Page 26

• Manufacturer Part Number: PI7C9X7952AFDE
• Description: IC PCIE-TO-UART BRIDGE 128LQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X7952AFDE

• Applications: PCIe-to-Uart Bridge
• Interface: Advanced Configuration Power Interface (ACPI)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.5.
6.2.6.
6.2.7.
6.2.8.
September 2009 – Revision 1.3
Pericom Semiconductor
REVISION ID REGISTER – OFFSET 08h
CLASS CODE REGISTER – OFFSET 08h
CACHE LINE REGISTER – OFFSET 0Ch
MASTER LATENCY TIMER REGISTER – OFFSET 0Ch
BIT
20
21
22
23
24
26:25
27
28
29
30
31
BIT
7:0
BIT
15:8
23:16
31:24
BIT
7:0
BIT
15:8
FUNCTION
Revision
FUNCTION
Cache Line Size
FUNCTION
Capabilities List
66MHz Capable
Reserved
Fast Back-to-Back
Capable
Master Data Parity
Error
DEVSEL# Timing
Signaled Target
Abort
Received Target
Abort
Received Master
Abort
Signaled System
Error
Detected Parity
Error
FUNCTION
Latency timer
FUNCTION
Programming
Interface
Sub-Class Code
Base Class Code
09-0087
RO
TYPE
TYPE
TYPE
TYPE
TYPE
RWC
RWC
RWC
RWC
RWC
RWC
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
Page 26 of 68
DESCRIPTION
be changed by auto-loading from EEPROM.
Reset to 00h.
DESCRIPTION
The cache line size register is set by the system firmware and the
operating system to system cache line size. This field is implemented
by PCI Express devices as a RW field for legacy compatibility
purposes but has no impact on any PCI Express device functionality.
Reset to 00h.
Indicates revision number of the I/O bridge. The default value may
DESCRIPTION
Does not apply to PCI Express. Must be hardwired to 00h.
DESCRIPTION
Reset to 0b.
Set to 1 to enable support for the capability list (offset 34h is the
pointer to the data structure)
Reset to 1b.
Does not apply to PCI Express. Must be hardwired to 0b.
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
It is not implemented. Hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Set to 1 (by a completer) whenever completing a request in the I/O
bridge side using Completer Abort Completion Status.
Reset to 0b.
It is not implemented. Hardwired to 0b.
It is not implemented. Hardwired to 0b.
Set to 1 when the I/O bridge sends an ERR_FATAL or
ERR_NONFATAL Message, and the SERR Enable bit in the
Command register is 1.
Reset to 0b.
Set to 1 whenever the I/O bridge receives a Poisoned TLP.
Reset to 0b.
DESCRIPTION
Read as 02h to indicate no programming interfaces have been
defined for PCI-to-PCI bridges
Read as 00h to indicate device is PCI-to-PCI bridge
Read as 07h to indicate device is a bridge device
PCI Express® Dual UART
PI7C9X7952
Datasheet