PI7C9X7952AFDE Pericom Semiconductor, PI7C9X7952AFDE Datasheet - Page 51

• Manufacturer Part Number: PI7C9X7952AFDE
• Description: IC PCIE-TO-UART BRIDGE 128LQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X7952AFDE

• Applications: PCIe-to-Uart Bridge
• Interface: Advanced Configuration Power Interface (ACPI)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2.2.
7.2.3.
7.2.4.
September 2009 – Revision 1.3
Pericom Semiconductor
TRANSMIT HOLDING REGISTER – OFFSET 00h
INTERRUPT ENABLE REGISTER – OFFSET 01h
INTERRUPT STATUS REGISTER – OFFSET 02h
BIT
7:0
BIT
0
1
2
3
4
5
6
7
BIT
7:0
Priority
Level
1
2
3
4
5
FUNCTION
Tx Holding
FUNCTION
Rx Data Available
Interrupt
Tx Empty Interrupt
Rx Error Status
Modem Status
Interrupt
Xoff/Special
character interrupt
RTS Interrupt
CTS Interrupt
Reserved
FUNCTION
Interrupt Status
Interrupt Status Bits
BIT-7
1
1
1
1
1
09-0087
BIT-6
1
1
1
1
1
BIT-5
0
0
0
0
0
WO
RW
RW
RW
RW
RW
RW
RW
RW
RO
TYPE
TYPE
TYPE
Page 51 of 68
BIT-4
0
0
0
0
0
DESCRIPTION
When data are written to the Transmit Holding Register (THR),
they are written to the bottom of the transmitter’s associated
FIFOs, which holds a queue of data to be transmitted by the
transmitter.
Data written to the THR when the FIFOs are full are lost. The
Line Status Register (LSR) indicates the full or empty status of
the FIFOs.
Reset to 00h.
DESCRIPTION
0b: Disable the Receive Data Ready Interrupt
1b: Enable the Receive Data Ready Interrupt
Reset to 0b.
0b: Disable the Transmit Holding Register Empty Interrupt
1b: Enable the Transmit Holding Register Empty Interrupt
Reset to 0b.
0b: Disable the Receive Line Status Interrupt
1b: Enable the Receive Line Status Interrupt
Reset to 0b.
0b: Disable the Modem Status Register Interrupt
1b: Enable the Modem Status Register Interrupt
Reset to 0b.
0b: Disable the Software Flow Control Interrupt
1b: Enable the Software Flow Control Interrupt
Reset to 0b.
0b: Disable RTS/DTR Interrupt
1b: Enable RTS/DTR Interrupt
Reset to 0b.
0b: Disable CTS/DSR interrupt
1b: Enable CTS/DSR interrupt
Reset to 0b.
Reset to 0b.
DESCRIPTION
0b: An interrupt is pending
1b: No interrupt pending
Reset to C1h.
BIT-3
0
0
1
0
0
BIT-2
1
1
1
0
0
BIT-1
1
0
0
1
0
BIT-0
0
0
0
0
0
PCI Express® Dual UART
Interrupt Source
Rx data error
Rx data available
Rx time-out
Tx FIFO empty
Modem status change
PI7C9X7952
Datasheet