PI7C9X7952AFDE Pericom Semiconductor, PI7C9X7952AFDE Datasheet - Page 55

no-image

PI7C9X7952AFDE

Manufacturer Part Number
PI7C9X7952AFDE
Description
IC PCIE-TO-UART BRIDGE 128LQFP
Manufacturer
Pericom Semiconductor
Datasheets

Specifications of PI7C9X7952AFDE

Applications
PCIe-to-Uart Bridge
Interface
Advanced Configuration Power Interface (ACPI)
Voltage - Supply
1.8V, 3.3V
Package / Case
128-LQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PI7C9X7952AFDE
Manufacturer:
Pericom
Quantity:
100
Part Number:
PI7C9X7952AFDE
Manufacturer:
Pericom
Quantity:
10 000
Part Number:
PI7C9X7952AFDE
Manufacturer:
PERICOM
Quantity:
20 000
7.2.10. SPECIAL FUNCTION REGISTER – OFFSET 07h
7.2.11. DIVISOR LATCH LOW REGISTER – OFFSET 08h
7.2.12. DIVISOR LATCH HIGH REGISTER – OFFSET 09h
7.2.13. ENHANCED FUNCTION REGISTER – OFFSET 0Ah
September 2009 – Revision 1.3
Pericom Semiconductor
BIT
5
6
7
BIT
0
1
2
3
4
5
6
7
BIT
7:0
BIT
7:0
BIT
1:0
FUNCTION
DSR
RI
DCD
FUNCTION
Force Transmission
Auto DSR and
DTR Flow Control
Reserved
Reserved
Reserved
950 Mode
RFD / LSR
Counter Select
TFD / SCR Select
FUNCTION
Divisor Low
FUNCTION
Divisor High
FUNCTION
In-Band Receive
Flow Control Mode
09-0087
RO
RO
RO
RW
RW
RO
RO
RW
RW
RW
RW
RW
RW
RW
TYPE
TYPE
TYPE
TYPE
TYPE
Page 55 of 68
DESCRIPTION
0b: The DSR input state is the logic 0
1b: The DSR input state is the logic 1
Reset to 0b.
The input state of RI pin
Reset to 0b.
The input state of DCD pin
Reset to 0b.
DESCRIPTION
Forces transmitter to always to transmit data.
1b: Enabled
0b: Disabled
Reset to 0b.
Auto DSR and DTR flow control enable
1b: Enables DSR and DTR auto flow control
0b: Disables DSR and DTR auto flow control
Reset to 0b.
Reset to 0b.
Reset to 0b.
Reset to 0b.
1b: Enables 950 mode
0b: Non-950 mode
Reset to 0b.
1b: OFFSET 15 bit[7:0] acts as the Line Status Register Counter
0b: OFFSET 15 bit[7:0] acts as the Receive FIFO Data Counter
Reset to 0b.
1b: OFFSET 16 bit[7:0] acts as the Transmit FIFO Data Counter
0b: OFFSET 16 bit[7:0] acts as the Sample Clock Register
Reset to 0b.
DESCRIPTION
Lower-part of the divisor register
Reset to 00h.
DESCRIPTION
Higher-part of the divisor register
Reset to 00h.
DESCRIPTION
When in-band receive flow control is enabled, the UART
compares the received data with the programmed XOFF
PCI Express® Dual UART
PI7C9X7952
Datasheet

Related parts for PI7C9X7952AFDE