PCA9541D/03,112 NXP Semiconductors, PCA9541D/03,112 Datasheet - Page 13
![IC I2C 2:1 SELECTOR 16SOIC](/photos/6/52/65286/16-soic_sot109-1_sml.jpg)
PCA9541D/03,112
Manufacturer Part Number
PCA9541D/03,112
Description
IC I2C 2:1 SELECTOR 16SOIC
Manufacturer
NXP Semiconductors
Datasheet
1.PCA9541BS03118.pdf
(41 pages)
Specifications of PCA9541D/03,112
Package / Case
16-SOIC (3.9mm Width)
Applications
2-Channel I²C Multiplexer
Interface
I²C, SMBus
Voltage - Supply
2.3 V ~ 5.5 V
Mounting Type
Surface Mount
Logic Family
PCA9541
Operating Supply Voltage
2.3 V to 5.5 V
Power Dissipation
400 mW
Operating Temperature Range
- 40 C to + 85 C
Input Voltage
7 V
Logic Type
I2C Bus
Maximum Clock Frequency
400 KHz
Mounting Style
SMD/SMT
Output Current
25 mA
Output Voltage
2.3 V to 5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935273317112
PCA9541D/03
PCA9541D/03
PCA9541D/03
PCA9541D/03
NXP Semiconductors
Table 11.
PCA9541_7
Product data sheet
Type version
PCA9541/01
PCA9541/03
Default Control Register values
Master
MST_0
MST_1
MST_0
MST_1
Table 12
master device wants to take control of the I
function of the current I
Control Register.
Current status of the I
NBUSON is one of the following:
‘I
‘I
Remark: Only the 4 LSBs of the Control Register are described in
those bits control the I
application and are not discussed in the table.
The read sequence is performed by the master as:
S - 111xxxx0 - 000x0001 - Sr - 111xxxx1 - DataRead - P
The write sequence is performed by the master as:
S - 111xxxx0 - 000x0001 - DataWritten - P
2
2
•
•
•
•
Bit 7
NTESTON TESTON
C-bus off’ means that upstream and downstream channels are not connected together.
C-bus on’ means that upstream and downstream channels are connected together.
The master reading its Control Register does not have control and the I
The master reading its Control Register does not have control and the I
The master reading its Control Register has control and the I
The master reading its Control Register has control and the I
0
0
0
0
describes which command needs to be written to the Control Register when a
Bit 6
0
0
0
0
2
2
C-bus is determined by the bits MYBUS, NMYBUS, BUSON and
2
C-bus control. The logic value for the 4 MSBs is specific to the
Bit 5
not used
C-bus control status performed after an initial reading of the
Rev. 07 — 2 July 2009
2-to-1 I
0
0
0
0
2
C-bus master selector with interrupt logic and reset
Bit 4
BUSINIT
0
0
0
0
2
C-bus. Byte written to the Control Register is a
Bit 3
NBUSON
0
1
0
0
Bit 2
BUSON
1
0
0
0
2
2
C-bus is off.
C-bus is on.
Table 12
Bit 1
NMYBUS
PCA9541
© NXP B.V. 2009. All rights reserved.
0
1
0
1
2
2
since only
C-bus is off.
C-bus is on.
Bit 0
MYBUS
13 of 41
0
0
0
0