W83627EHG Nuvoton Technology Corporation of America, W83627EHG Datasheet - Page 15

• Manufacturer Part Number: W83627EHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627EHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5. PIN DESCRIPTION
Note: Please refer to Section 8.2 DC CHARACTERISTICS for details.
AOUT
AIN
IN
IN
IN
IN
IN
IN
I/O
I/O
I/OD
I/OD
I/OD
OUT
OUT
OUT
OD
OD
OD
5.1
IOCLK
PME#
PCICLK
LDRQ#
SERIRQ
LAD[3:0]
LFRAME#
LRESET#
cs
t
td
ts
tsp3
tu
8t
12t
8
12
24
SYMBOL
12ts
16cs
24t
8
12
24
LPC Interface
- Analog output pin
- Analog input pin
- CMOS level Schmitt-triggered input pin
- TTL level input pin
- TTL level input pin with internal pull down resistor
- TTL level Schmitt-triggered input pin
- 3.3V TTL level Schmitt-triggered input pin
- TTL level input pin with internal pull up resistor
- TTL level bi-directional pin with 8 mA source-sink capability
-3.3V TTL level bi-directional pin with 12 mA source-sink capability
- 3.3V TTL level bi-directional Schmitt-triggered pin. Open-drain output with 12 mA sink capability
- CMOS level Schmitt-triggered bi-directional pin. Open-drain output with 16 mA sink capability
- TTL level bi-directional pin. Open-drain output with 24 mA sink capability
- TTL level output pin with 8 mA source-sink capability
-3.3V TTL level output pin with 12 mA source-sink capability
- TTL level output pin with 24 mA source-sink capability
- Open-drain output pin with 8 mA sink capability
- Open-drain output pin with 12 mA sink capability
- Open-drain output pin with 24 mA sink capability
18
86
21
22
23
24-
27
29
30
PIN
IN
OD
IN
O
I/OD
I/O
IN
IN
12
t
ts
ts
ts
12t
12
I/O
12t
System clock input, which is selective by the register according
to the input frequency either 24MHz or 48MHz. Default is
48MHz.
Generated PME event.
PCI clock 33 MHz input.
Encoded DMA Request signal.
Serial IRQ Input/Output.
These signal lines communicate address, control, and data
information over the LPC bus between a host and a peripheral.
Indicates start of a new cycle or termination of a broken cycle.
Reset signal. It can connect to PCIRST# signal on the host.
W83627EHF/EF, W83627EHG/EG
- 9 -
FUNCTION
Publication Release Date: Nov. 2006
Revision 1.3