W83627EHG Nuvoton Technology Corporation of America, W83627EHG Datasheet - Page 99

• Manufacturer Part Number: W83627EHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627EHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CR 24h. (Global Option; Default 0100_0ss0b)
CR 25h. (Interface tri-state Enable; Default 00h)
7~6
2~1
BIT
BIT
7
6
5
4
3
2
1
0
5
4
3
0
Reserved.
Reserved.
Reserved.
Reserved.
READ / WRITE
READ / WRITE
Read Only
R / W
R / W
R / W
R / W
R / W
R / W
R / W
R / W
R / W
CLKSEL => Input clock rate selection
= 0
= 1
Enable SYSFANOUT as Output Buffer (For H version only)
=0 SYSFANOUT is Open-Drain. (Default)
=1 SYSFANOUT can drive logical high or logical low.
Enable CPUFANOUT0 as Output Buffer
=0 CPUFANOUT0 is Open-Drain. (Default)
=1 CPUFANOUT0 can drive logical high or logical low.
ENKBC => Enable keyboard controller
= 0
= 1
This bit is read only, and set/reset by power-on strapping pin (PIN54;
SOUTA).
ENROM => Enable Serial FHW
= 0
= 1
This bit set/reset by power-on strapping pin (PIN52; DTRA).
PNPCVS =>
= 0
= 1
value.
URBTRI
URATRI
PRTTRI
FDCTRI.
The clock input on pin18 is 24MHz.
The clock input on pin18 is 48MHz. (Default)
KBC is disabled after hardware reset.
KBC is enabled after hardware reset.
ROM is disabled after hardware reset.
ROM is enabled after hardware reset.
The compatible PNP address select registers have default values.
The compatible PNP address select registers have no default
W83627EHF/EF, W83627EHG/EG
- 93 -
DESCRIPTION
DESCRIPTION
s: value by strapping
Publication Release Date: Nov. 2006
(For H version only)
Revision 1.3