PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet
PI7C8152BMAE
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PI7C8152A & PI7C8152B 2-Port PCI-to-PCI Bridge 2380 Bering Drive, San Jose, CA 95131 Telephone: 1-877-PERICOM, (1-877-737-4266) Email: Internet: http://www.pericom.com REVISION 1.11 Fax: 408-435-1100 solutions@pericom.com ...
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... Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use ...
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REVISION HISTORY Date Revision Number 08/13/03 0.01 First draft of datasheet 08/14/03 0.02 09/19/03 1.00 Datasheet release to the web 09/25/03 1.10 10/16/03 1.11 Description Revised bit[4] offset 48h Revised revision ID register bit[7:0] offset 08h from ...
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This page intentionally left blank. PI7C8152A & PI7C8152B 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Page October 16, 2003 – Revision 1.11 ...
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TABLE OF CONTENTS 1 INTRODUCTION .............................................................................................................................. 11 2 SIGNAL DEFINITIONS ................................................................................................................... 12 2 ............................................................................................................................... 12 IGNAL YPES 2.2 S ........................................................................................................................................ 12 IGNALS 2.2.1 PRIMARY BUS INTERFACE SIGNALS .......................................................................... 12 2.2.3 CLOCK SIGNALS ............................................................................................................... 15 2.2.4 MISCELLANEOUS SIGNALS........................................................................................... 15 ...
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VGA SUPPORT ........................................................................................................................... 41 4.4.1 VGA MODE......................................................................................................................... 41 4.4.2 VGA SNOOP MODE........................................................................................................... 42 5 TRANSACTION ORDERING.......................................................................................................... 42 5.1 TRANSACTIONS GOVERNED BY ORDERING RULES ........................................................ 42 5.2 GENERAL ORDERING GUIDELINES...................................................................................... 43 5.3 ORDERING RULES .................................................................................................................... 44 5.4 DATA SYNCHRONIZATION .................................................................................................... ...
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REVISION ID REGISTER – OFFSET 08h ...................................................................... 70 12.1.6 CLASS CODE REGISTER – OFFSET 08h....................................................................... 70 12.1.7 CACHE LINE SIZE REGISTER – OFFSET 0Ch ............................................................ 70 12.1.8 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ........................................... 70 12.1.9 HEADER TYPE ...
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PCI SIGNALING TIMING............................................................................................. 88 14.5 33MHZ PCI SIGNALING TIMING............................................................................................. 88 14.6 RESET TIMING........................................................................................................................... 88 14.7 POWER CONSUMPTION........................................................................................................... 89 15 PACKAGE INFORMATION........................................................................................................ 89 15.1 160-PIN MQFP PACKAGE DIAGRAM ..................................................................................... 89 15.2 PART NUMBER ORDERING INFORMATION ........................................................................ 89 LIST OF ...
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... INTRODUCTION Product Description The PI7C8152A and PI7C8152B (PI7C8152x) are Pericom Semiconductor’s PCI-to-PCI Bridge that are designed to be fully compliant with the 32-bit, 66MHz implementation of the PCI Local Bus Specification, Revision 2.2. The PI7C8152B supports both synchronous and asynchronous bus transactions between devices on the Primary Bus and the Secondary Buses operating up to 66MHz ...
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SIGNAL DEFINITIONS 2.1 Signal Types Signal Type STS OD 2.2 Signals Note: Signal names that end with “_L” are active LOW. 2.2.1 PRIMARY BUS INTERFACE SIGNALS Name P_AD[31:0] P_CBE[3:0] P_PAR P_FRAME_L Description Input Only Output ...
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Name Pin # P_IRDY_L 97 P_TRDY_L 99 P_DEVSEL_L 100 P_STOP_L 101 P_LOCK_L 102 P_IDSEL 83 P_PERR_L 104 P_SERR_L 105 P_REQ_L 69 P_GNT_L 68 P_RESET_L 64 Page PI7C8152A & PI7C8152B 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Type Description STS ...
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SECONDARY BUS INTERFACE SIGNALS Name S_AD[31:0] S_CBE[3:0] S_PAR S_FRAME_L S_IRDY_L S_TRDY_L S_DEVSEL_L S_STOP_L S_LOCK_L Pin # Type Description 36, 35, 33, 32, 31, TS Secondary Address/Data: Multiplexed address and data 29, 28, 26, 24, 22, bus. Address is indicated ...
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Name S_PERR_L S_SERR_L S_REQ_L[3:0] S_GNT_L[3:0] S_RESET_L S_CFN_L 2.2.3 CLOCK SIGNALS Name P_CLK S_CLKIN S_CLKOUT[4:0] 2.2.4 MISCELLANEOUS SIGNALS Name P_VIO Pin # Type Description 4 STS Secondary Parity Error (Active LOW): Asserted when a data parity error is detected for data ...
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S_VIO BPCCE SCAN_EN SCAN_TM_L 2.2.5 POWER AND GROUND Name VDD VSS 2.3 PIN LIST – 160-PIN MQFP Table 2-1 PIN LIST – 160-PIN MQFP Pin Name Number 1 VSS 4 S_PERR_L 7 S_DEVSEL_L 10 S_IRDY_L 13 S_CBE_L[2] 16 S_AD[17] 19 ...
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Pin Name Number 49 S_CFN_L 52 S_VIO 55 S_CLKOUT[1] 58 VSS 61 S_CLKOUT[4] 64 P_RESET_L 67 P_VIO 70 P_AD[31] 73 P_AD[29] 76 P_AD[27] 79 P_AD[24] 82 P_CBE_L[3] 85 P_AD[22] 88 P_AD[20] 91 P_AD[18] 94 VSS 97 P_IRDY_L 100 P_DEVSEL_L 103 ...
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Table 3-1 PCI TRANSACTIONS Types of Transactions 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0100 Reserved 0101 Reserved 0110 Memory Read 0111 Memory Write 1000 Reserved 1001 Reserved 1010 Configuration Read 1011 Configuration Write 1100 ...
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CBE_L[3:0] lines, and the high 32 address bits on the AD[31:0] lines. In this way, 64-bit addressing can be supported on 32-bit PCI buses. The PCI-to-PCI Bridge Architecture Specification ...
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MEMORY WRITE TRANSACTIONS Posted write forwarding is used for “Memory Write” and “Memory Write and Invalidate” transactions. When PI7C8152x determines that a memory write transaction forwarded across the bridge, PI7C8152x asserts DEVSEL_L with medium decode timing ...
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MEMORY WRITE AND INVALIDATE Posted write forwarding is used for Memory Write and Invalidate transactions. The PI7C8152x disconnects Memory Write and Invalidate commands at aligned cache line boundaries. The cache line size value in the cache line size register ...
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PI7C8152x responds to target termination during delayed write transactions. PI7C8152x implements a discard timer that starts counting when the delayed write completion is at the head of the delayed transaction completion queue. The initial value of this ...
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FAST BACK-TO-BACK WRITE TRANSACTIONS PI7C8152x is capable of decoding and forwarding fast back-to-back write transactions. When PI7C8152x cannot accept the second transaction because of buffer space limitations, it returns a target retry to the initiator. The fast back-to-back enable ...
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If these locations are mapped in memory space, use the memory read command and map the target into non-prefetchable (memory-mapped I/O) memory space to use non-prefetching behavior. 3.7.3 READ PREFETCH ADDRESS BOUNDARIES PI7C8152x imposes internal read address boundaries on ...
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PI7C8152x accepts a delayed read request by sampling the read address, read ...
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When the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read transaction on the target ...
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To support hierarchical PCI bus systems, two types of configuration transactions are specified: Type 0 and Type 1. Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type 0 ...
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PI7C8152x performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. PI7C8152x must convert the configuration command to a ...
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PI7C8152x can assert unique address lines to be used as IDSEL signals for devices on the secondary bus, for device numbers ranging from 0 through 15. Because of electrical loading constraints of the PCI ...
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The PI7C8152x forwards Type 1 to Type 1 configuration write transactions as delayed transactions. Type 1 to Type 1 configuration write transactions are limited to a single data transfer. 3.8.4 SPECIAL CYCLES The Type 1 configuration mechanism is used to ...
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Master abort A master abort occurs when no target response is detected. When the initiator does not detect a DEVSEL_L from the target within five clock cycles after asserting FRAME_L, the initiator terminates the transaction with a master abort. ...
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The target terminates the transaction with a retry, disconnect, or target abort. If PI7C8152x is delivering posted write data when it terminates the transaction because the master latency timer expires, it initiates another transaction to deliver the remaining write ...
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PI7C8152x handles these terminations in different ways, depending on the type of transaction being performed. 3.9.3.1 DELAYED WRITE TARGET TERMINATION RESPONSE When PI7C8152x initiates a delayed write transaction, the type of target termination received from the target can be passed ...
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Note that when a target retry or target disconnect is returned and posted write data associated with that transaction remains in the write buffers, PI7C8152x initiates another write transaction to attempt to deliver the rest of the write data. If ...
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TARGET TERMINATION INITIATED BY PI7C8152x PI7C8152x can return a target retry, target disconnect, or target abort to an initiator for reasons other than detection of that condition at the target interface. 3.9.4.1 TARGET RETRY PI7C8152x returns a target retry ...
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Use more than 16 clocks to accept this transaction. For posted write transactions: ! The posted write data buffer does not have enough space for address and at least one DWORD of write data locked sequence is ...
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ADDRESS RANGES PI7C8152x uses the following address ranges that determine which I/O and memory transactions are forwarded from the primary PCI bus to the secondary PCI bus, and from the secondary bus to the primary bus: ! Two 32-bit ...
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VGA snoop bit before setting I/O enable and master enable bits, and change them subsequently only when the primary and secondary PCI buses are idle. 4.2.1 I/O BASE AND LIMIT ADDRESS REGISTER PI7C8152x implements one set of ...
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When the ISA enable bit is set, PI7C8152x does not forward downstream any I/O transactions addressing the top 768 bytes of each aligned 1KB block. Only those transactions addressing the bottom 256 bytes of an aligned 1KB block inside the ...
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The memory-mapped I/O base address and memory-mapped I/O limit address registers define an address range that PI7C8152x uses to determine when to forward memory commands. PI7C8152x forwards a memory transaction from the primary to the secondary interface if the transaction ...
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The prefetchable memory range supports 64-bit addressing and provides additional registers to define the upper 32 bits of the memory address range, the prefetchable memory base address upper 32 bits register, and the prefetchable memory limit address upper 32 bits ...
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The VGA frame buffer consists of the following memory address range: 000A 0000h–000B FFFFh Read transactions to frame buffer memory are treated as non-prefetchable. PI7C8152x requests only a single data transfer from the target, and read byte enable bits are ...
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Delayed write request transactions, comprised of I/O write and configuration write transactions. Delayed write requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. A delayed write transaction must complete on the ...
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If more than one delayed transaction is initiated, the initiator should repeat all delayed transaction requests, using some fairness algorithm. Repeating a delayed transaction cannot be contingent on completion of another ...
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A delayed read request traveling in the same direction as a previously queued posted write transaction must push the posted write data ahead of it. The posted write transaction must complete on the target bus before the delayed read ...
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PI7C8152x always attempts to be transparent when reporting errors, but this is not always possible, given the presence of posted data and delayed transactions. To support error ...
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DATA PARITY ERRORS When forwarding transactions, PI7C8152x attempts to pass the data parity condition from one interface to the other unchanged, whenever possible, to allow the master and target devices to handle the error condition. The following sections describe, ...
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PI7C8152x asserts P_PERR_L two cycles following the data transfer, if the primary interface parity error response bit is set in the command register. ! PI7C8152x sets the detected parity error bit in the primary status register. ! PI7C8152x sets ...
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Note: If parity checking is turned off and data parity errors have occurred for queued or subsequent delayed write transactions on the initiator bus possible that the initiator’s re-attempts of the write transaction may not match the original ...
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PI7C8152x sets the secondary interface parity-error-detected bit in the secondary status register. ! Because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue. For downstream transactions, ...
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Similarly, during upstream posted write transactions, when PI7C8152x responds as a target, it detects a data parity error on the initiator (secondary) bus, the following events occur: ! PI7C8152x asserts S_PERR_L two cycles after the data transfer, if the parity ...
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The parity error response bit is set in the command register of the primary interface. ! PI7C8152x has not detected the parity error on the secondary (initiator) bus, which the parity error is not forwarded from the secondary bus ...
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Secondary Transaction Type Detected Parity Error Bit 0 Read 0 Read 0 Posted Write 0 Posted Write 0 Posted Write 1 Posted Write 0 Delayed Write 0 Delayed Write 0 Delayed Write 1 Delayed Write X = don’t care Table ...
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Table 6-4 SETTING SECONDARY BUS MASTER DATA PARITY ERROR DETECTED BIT Secondary Transaction Type Detected Parity Detected Bit 0 Read 1 Read 0 Read 0 Read 0 Posted Write 1 Posted Write 0 Posted Write 0 Posted Write 0 Delayed ...
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The parity error response bit must be set in the bridge control register of secondary interface. ! PI7C8152x detects a data parity error on the secondary bus or detects P_PERR_L asserted during the completion phase of an upstream delayed ...
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The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. 3 The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus. 6.4 SYSTEM ERROR (SERR_L) ...
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EXCLUSIVE ACCESS This chapter describes the use of the LOCK_L signal to implement exclusive access to a target for transactions that cross PI7C8152x. 7.1 CONCURRENT LOCKS The primary and secondary bus lock mechanisms operate concurrently except when a locked ...
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When the locked delayed memory read request is queued, PI7C8152x does not queue any more transactions until the locked sequence is finished. PI7C8152x signals a target retry to all transactions initiated subsequent to the locked read transaction that are intended ...
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LOCKED TRANSACTION IN UPSTREAM DIRECTION PI7C8152x ignores upstream lock and transactions. PI7C8152x will pass these transactions as normal transactions without lock established. 7.3 ENDING EXCLUSIVE ACCESS After the lock has been acquired on both initiator and target buses, PI7C8152x ...
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PCI BUS ARBITRATION PI7C8152x must arbitrate for use of the primary bus when forwarding upstream transactions. Also, it must arbitrate for use of the secondary bus when forwarding downstream transactions. The arbiter for the primary bus resides external to ...
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The low priority group as a whole represents one entry in the high priority group; that is, if the high priority group consists of n masters, then in at least every n+1 transactions the ...
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To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one grant signal in the same PCI cycle in which it de-asserts another. It de-asserts one grant and asserts the next grant, no earlier than ...
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If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last master that used the PCI bus. That is, PI7C8152x keeps the secondary bus grant asserted to a particular master until a new secondary ...
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P_CLK is the input source for the primary clock and S_CLKIN is the input source for the secondary clock. The S_CLKOUT[4:0] outputs cannot be used for any external secondary bus devices in asynchronous mode. Instead, devices on the secondary bus ...
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PME_L signals are routed from downstream devices around PCI-to-PCI bridges. PME_L signals do not pass through PCI-to-PCI bridges. 11 RESET This chapter describes the primary interface, secondary interface, and chip reset mechanisms. 11.1 PRIMARY INTERFACE RESET PI7C8152x has a reset ...
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When S_RESET_L is asserted by means of the secondary reset bit, PI7C8152x remains accessible during secondary interface reset and continues to respond to accesses to its configuration space from the primary interface. 11.3 CHIP RESET The chip reset bit in ...
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CONFIGURATION REGISTER 31-24 Device ID Primary Status Reserved Secondary Latency Timer Secondary Status Memory Limit Address Prefetchable Memory Limit Address I/O Limit Address Upper 16-bit Bridge Control Arbiter Control Reserved Secondary Bus Arbiter Preemption Control Reserved Reserved Reserved Secondary ...
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COMMAND REGISTER – OFFSET 04h Bit Function 0 I/O Space Enable Memory Space 1 Enable Bus Master 2 Enable Special Cycle 3 Enable Memory Write 4 And Invalidate Enable VGA Palette 5 Snoop Enable Parity Error 6 Response Wait ...
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Bit Function P_SERR_L 8 enable Fast Back-to- 9 Back Enable 15:10 Reserved 12.1.4 PRIMARY STATUS REGISTER – OFFSET 04h Bit Function 19:16 Reserved 20 Capabilities List 21 66MHz Capable 22 Reserved 23 Fast Back-to- Back Capable 24 Data Parity Error ...
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Bit Function 31 Detected Parity Error 12.1.5 REVISION ID REGISTER – OFFSET 08h Bit Function 7:0 Revision 12.1.6 CLASS CODE REGISTER – OFFSET 08h Bit Function 15:8 Programming Interface 23:16 Sub-Class Code 31:24 Base Class Code 12.1.7 CACHE LINE SIZE ...
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PRIMARY BUS NUMBER REGISTSER – OFFSET 18h Bit Function 7:0 Primary Bus Number 12.1.11 SECONDARY BUS NUMBER REGISTER – OFFSET 18h Bit Function 15:8 Secondary Bus Number 12.1.12 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h Bit Function 23:16 Subordinate ...
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I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch Bit Function 11:8 32-bit Indicator 15:12 I/O Limit Address [15:12] 12.1.16 SECONDARY STATUS REGISTER – OFFSET 1Ch Bit Function 20:16 Reserved 21 66MHz Capable 22 Reserved Fast Back-to- 23 Back Capable Data ...
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MEMORY BASE ADDRESS REGISTER – OFFSET 20h Bit Function 3:0 Reserved 15:4 Memory Base Address [15:4] 12.1.18 MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h Bit Function 19:16 Reserved 31:20 Memory Limit Address [31:20] 12.1.19 PEFETCHABLE MEMORY BASE ADDRESS REGISTER ...
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Bit Function 31:20 Prefetchable Memory Limit Address [31:20] 12.1.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h Bit Function 31:0 Prefetchable Memory Base Address, Upper 32-bits [63:32] 12.1.22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch ...
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INTERRUPT PIN REGISTER – OFFSET 3Ch Bit Function 15:8 Interrupt Pin 12.1.27 BRIDGE CONTROL REGISTER – OFFSET 3Ch Bit Function 16 Parity Error Response 17 S_SERR_L enable 18 ISA enable 19 VGA enable 20 Reserved 21 Master Abort Mode ...
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Bit Function 22 Secondary Interface Reset 23 Fast Back-to- Back Enable 24 Primary Master Timeout 25 Secondary Master Timeout 26 Master Timeout Status 27 Discard Timer P_SERR_L enable 31-28 Reserved 12.1.28 DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h Bit ...
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Bit Function Type Description 1 Memory Write R/W Controls when the bridge (as a target) disconnects memory write Disconnect transactions. Control 0: memory write disconnects at 4KB aligned address boundary 1: memory write disconnects at cache line aligned address boundary ...
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ARBITER CONTROL REGISTER – OFFSET 40h Bit Function 24:16 Arbiter Control 25 Priority of Secondary Interface 31:26 Reserved 12.1.30 EXTENDED CHIP CONTROL REGISTER – OFFSET 48h Bit Function Memory Read 0 Flow Through Enable 1 Park 3:2 Reserved Memory ...
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SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET 4Ch Bit Function Secondary bus arbiter 31:28 preemption contorl 12.1.32 P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h Bit Function 0 Reserved Posted Write 1 Parity Error Posted Write 2 Non-Delivery Target ...
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Bit Function Master Abort On 4 Posted Write Delayed Write 5 Non-Delivery Delayed Read – Data From Target 7 Reserved 12.1.33 SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h Bit Function S_CLKOUT[0] 1:0 disable 3:2 Clock 1 disable 5:4 ...
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Bit Function 7:6 Clock 3 disable 8 Clock 4 disable 13:9 Reserved 15:14 Reserved 12.1.34 P_SERR_L STATUS REGISTER – OFFSET 68h Bit Function Address Parity 16 Error Posted Write 17 Data Parity Error Posted Write 18 Non-delivery Target Abort 19 ...
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Bit Function Type Description Controls PI7C8152x’s detection mechanism for matching memory read retry cycles from the initiator on the primary interface 0: exact matching memory read retry cycles from initiator on the Primary Memory primary interface 1 Read Command R/W ...
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Bit Function Primary Memory Write and 7 Invalidate Command Alias Disable Secondary Memory Write 8 and Invalidate Command Alias Disable Enable Long 9 Request Enable Secondary To 10 Hold Request Longer Enable Primary 11 To Hold Request Longer 15:12 Reserved ...
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SECONDARY MASTER TIMEOUT COUNTER – OFFSET 80h Bit Function Secondary 31:16 Timeout 12.1.38 CAPABILITY ID REGISTER – OFFSET DCh Bit Function Enhanced 7:0 Capabilities ID 12.1.39 NEXT ITEM POINTER REGISTER – OFFSET DCh Bit Function Next Item 15:8 Pointer ...
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Bit Function 8 PME_L Enable 12:9 Data Select 14:13 Data Scale 15 PME status 12.1.42 PPB SUPPORT EXTENSIONS REGISER – OFFSET E0h Bit Function 21:16 Reserved 22 B2_B3 Support Bus Power / 23 Clock Control Enable 13 BRIDGE BEHAVIOR A ...
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Initiator Master on Secondary 13.2 ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER) 13.2.1 MASTER ABORT Master abort indicates that when PI7C8152x acts as a master and receives no response (i.e., no target asserts DEVSEL_L or S_DEVSEL_L) from a target, the bridge ...
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ELECTRICAL AND TIMING SPECIFICATIONS 14.1 MAXIMUM RATINGS (Above which the useful life may be impaired. For user guidelines not tested). Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground Potentials (Inputs and AV DC Input Voltage Junction ...
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Figure 14-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS Symbol Parameter Tsu Input setup time to CLK – bused signals Tsu(ptp) Input setup time to CLK – point-to-point Th Input signal hold time from CLK Tval CLK to signal valid delay – ...
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POWER CONSUMPTION Parameter Power Consumption at 66MHz Supply Current PACKAGE INFORMATION 15.1 160-PIN MQFP PACKAGE DIAGRAM Figure 15-1 160-PIN MQFP PACKAGE OUTLINE Thermal characteristics can be found on the web: 15.2 PART NUMBER ORDERING INFORMATION Part ...
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PI7C8152A & PI7C8152B 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION NOTES: Page October 16, 2003 – Revision 1.11 ...