PI7C8152BMAE Pericom Semiconductor, PI7C8152BMAE Datasheet - Page 29
![IC PCI-PCI BRIDGE 2PORT 160-MQFP](/photos/6/93/69398/pi7c8152bmae_sml.jpg)
PI7C8152BMAE
Manufacturer Part Number
PI7C8152BMAE
Description
IC PCI-PCI BRIDGE 2PORT 160-MQFP
Manufacturer
Pericom Semiconductor
Datasheet
1.PI7C8152AMAE.pdf
(90 pages)
Specifications of PI7C8152BMAE
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
160-MQFP, 160-PQFP
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3 V to 3.6 V
Supply Current (max)
246 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PI7C8152BMAE
Manufacturer:
PERICOM
Quantity:
748
Part Number:
PI7C8152BMAE
Manufacturer:
PERICOM
Quantity:
20 000
3.8.3
PI7C8152x can assert up to 16 unique address lines to be used as IDSEL signals for
up to 16 devices on the secondary bus, for device numbers ranging from 0 through 15.
Because of electrical loading constraints of the PCI bus, more than 16 IDSEL signals
should not be necessary. However, if device numbers greater than 15 are desired, some
external method of generating IDSEL lines must be used, and no upper address bits are
then asserted. The configuration transaction is still translated and passed from the primary
bus to the secondary bus. If no IDSEL pin is asserted to a secondary device, the transaction
ends in a master abort.
PI7C8152x forwards Type 1 to Type 0 configuration read or write transactions as delayed
transactions. Type 1 to Type 0 configuration read or write transactions are limited to a
single 32-bit data transfer.
TYPE 1 TO TYPE 1 FORWARDING
Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism
when two or more levels of PCI-to-PCI bridges are used.
When PI7C8152x detects a Type 1 configuration transaction intended for a PCI bus
downstream from the secondary bus, PI7C8152x forwards the transaction unchanged to the
secondary bus. Ultimately, this transaction is translated to a Type 0 configuration command
or to a special cycle transaction by a downstream PCI-to-PCI bridge. Downstream Type 1
to Type 1 forwarding occurs when the following conditions are met during the address
phase:
!
!
!
PI7C8152x also supports Type 1 to Type 1 forwarding of configuration write transactions
upstream to support upstream special cycle generation. A Type 1 configuration command
is forwarded upstream when the following conditions are met:
!
!
!
!
!
The lowest two address bits are equal to 01b.
The bus number falls in the range defined by the lower limit (exclusive) in the
secondary bus number register and the upper limit (inclusive) in the subordinate bus
number register.
The bus command is a configuration read or write transaction.
The lowest two address bits are equal to 01b.
The bus number falls outside the range defined by the lower limit (inclusive)
in the secondary bus number register and the upper limit (inclusive) in the subordinate
bus number register.
The device number in address bits AD[15:11] is equal to 11111b.
The function number in address bits AD[10:8] is equal to 111b.
The bus command is a configuration write transaction.
Page 29 of 90
2-PORT PCI-TO-PCI BRIDGE
October 16, 2003 – Revision 1.11
ADVANCE INFORMATION
PI7C8152A & PI7C8152B