PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 15

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.2.3
SECONDARY BUS INTERFACE SIGNALS
Name
P_REQ64#
P_ACK64#
Name
S_AD[31:0]
S_CBE[3:0]
S_PAR
S_FRAME#
S_IRDY#
Pin #
AC14
AB14
Pin #
C3, A3, B3, C4, A4, B4, C5,
B5, A6, A7, D7, B7, A8,
B8, C8, A9, C13, B13, A13,
D13, C14, B14, C15, B15,
C16, B16, C17, B17, D17,
A17, B18, A18
C6, D9, C12, A15
B12
B9
C9
Page 15 of 112
Type
Type
STS
STS
STS
STS
TS
TS
TS
Description
Primary 64-bit Transfer Request: P_REQ64# is
asserted by the initiator to indicate that the initiator
is requesting a 64-bit data transfer. P_REQ64# has
the same timing as P_FRAME#. When P_REQ64#
is asserted LOW during reset, a 64-bit data path is
supported. When P_REQ64# is HIGH during reset,
bridge drives P_AD[63:32], P_CBE[7:4], and
P_PAR64 to valid logic levels. When deasserting,
P_REQ64# is driven to a deasserted state for 1 cycle
and then sustained by an external pull-up resistor.
Primary 64-bit Transfer Acknowledge:
P_ACK64# is asserted by the target only when
P_REQ64# is asserted by the initiator to indicate the
target’s ability to transfer data using 64 bits.
P_ACK64# has the same timing as P_DEVSEL#.
When deasserting, P_ACK64# is driven to a
deasserted state for 1 cycle and then is sustained by
an external pull-up resistor.
Description
Secondary Address/Data: Multiplexed address and
data bus. Address is indicated by S_FRAME#
assertion. Write data is stable and valid when
S_IRDY# is asserted and read data is stable and
valid when S_IRDY# is asserted. Data is
transferred on rising clock edges when both
S_IRDY# and S_TRDY# are asserted. During bus
idle, bridge drives S_AD[31:0] to a valid logic level
when S_GNT# is asserted respectively.
Secondary Command/Byte Enables: Multiplexed
command field and byte enable field. During
address phase, the initiator drives the transaction
type on these pins. The initiator then drives the byte
enables during data phases. During bus idle, bridge
drives S_CBE[3:0] to a valid logic level when the
internal grant is asserted.
Secondary Parity: S_PAR is an even parity of
S_AD[31:0] and S_CBE[3:0] (i.e. an even number
of 1’s). S_PAR is valid and stable one cycle after
the address phase (indicated by assertion of
S_FRAME#) for address parity. For write data
phases, S_PAR is valid one clock after S_IRDY# is
asserted. For read data phase, S_PAR is valid one
clock after S_TRDY# is asserted. Signal S_PAR is
tri-stated one cycle after the S_AD lines are tri-
stated. During bus idle, bridge drives S_PAR to a
valid logic level when the internal grant is asserted.
Secondary FRAME (Active LOW): Driven by the
initiator of a transaction to indicate the beginning
and duration of an access. The de-assertion of
S_FRAME# indicates the final data phase requested
by the initiator. Before being tri-stated, it is driven
to a de-asserted state for one cycle.
Secondary IRDY (Active LOW): Driven by the
initiator of a transaction to indicate its ability to
complete current data phase on the secondary side.
Once asserted in a data phase, it is not de-asserted
until the end of the data phase. Before tri-stated, it
is driven to a de-asserted state for one cycle.
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A