PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 7

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8
9
10
11
12
13
14
8.1
8.2
8.3
9.1
9.2
9.3
9.4
11.1
11.2
13.1
13.2
13.3
7.2.4
GENERAL PURPOSE I/O INTERFACE ...............................................................................................67
EEPROM INTERFACE............................................................................................................................70
VITAL PRODUCT DATA (VPD) ............................................................................................................72
CLOCKS.....................................................................................................................................................72
PCI POWER MANAGEMENT................................................................................................................72
RESET.........................................................................................................................................................74
CONFIGURATION REGISTERS ...........................................................................................................76
14.1.1
14.1.2
14.1.3
14.1.4
14.1.5
14.1.6
14.1.7
14.1.8
14.1.9
14.1.10
14.1.11
14.1.12
14.1.13
14.1.14
14.1.15
14.1.16
14.1.17
14.1.18
14.1.19
14.1.20
14.1.21
14.1.22
14.1.23
14.1.24
14.1.25
14.1.26
14.1.27
GPIO CONTROL REGISTERS.........................................................................................................68
SECONDARY CLOCK CONTROL..................................................................................................68
LIVE INSERTION .............................................................................................................................70
AUTO MODE EEPROM ACCESS ...................................................................................................70
EEPROM MODE AT RESET............................................................................................................71
EEPROM DATA STRUCTURE........................................................................................................71
EEPROM CONTENT ........................................................................................................................71
PRIMARY AND SECONDARY CLOCK INPUTS..........................................................................72
SECONDARY CLOCK OUTPUTS ..................................................................................................72
PRIMARY INTERFACE RESET ......................................................................................................74
SECONDARY INTERFACE RESET................................................................................................74
CHIP RESET......................................................................................................................................75
BUS PARKING ..............................................................................................................................67
SIGNAL TYPES.........................................................................................................................77
VENDOR ID REGISTER – OFFSET 00h .................................................................................77
DEVICE ID REGISTER – OFFSET 00h ...................................................................................77
COMMAND REGISTER – OFFSET 04h ..................................................................................77
STATUS REGISTER – OFFEST 04h.........................................................................................78
REVISION ID REGISTER – OFFSET 08h................................................................................79
CLASS CODE REGISTER – OFFSET 08h ...............................................................................79
CACHE LINE SIZE REGISTER – OFFSET 0Ch ......................................................................79
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch.......................................................79
HEADER TYPE REGISTER – OFFSET 0Ch............................................................................80
PRIMARY BUS NUMBER REGISTER – OFFSET 18h ............................................................80
SECONDARY BUS NUMBER REGISTER – OFFSET 18h ......................................................80
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h ..................................................80
SECONDARY LATENCY TIMER – OFFSET 18h ....................................................................80
I/O BASE REGISTER – OFFSET 1Ch ......................................................................................80
I/O LIMIT REGISTER – OFFSET 1Ch.....................................................................................81
SECONDARY STATUS REGISTER – OFFSET 1Ch ................................................................81
MEMORY BASE REGISTER – OFFSET 20h ...........................................................................82
MEMORY LIMIT REGISTER – OFFSET 20h ..........................................................................82
PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h ...........................82
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h ..........................83
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h83
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch
83
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h .........................................83
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h........................................83
CAPABILITY POINTER REGISTER – OFFSET 34h ...............................................................84
INTERRUPT LINE REGISTER – OFFSET 3Ch .......................................................................84
Page 7 of 112
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A