PI7C8154ANAE Pericom Semiconductor, PI7C8154ANAE Datasheet - Page 92

• Manufacturer Part Number: PI7C8154ANAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.44
14.1.45
GPIO DATA AND CONTROL REGISTER – OFFSET 64h
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h
Bit
11:8
15:12
19:16
23:20
27:24
31:28
Bit
1:0
3:2
Function
GPIO output
write-1-to-clear
GPIO output
write-1-to-set
GPIO output
enable write-1-
to-clear
GPIO output
enable write-1-
to-set
Reserved
GPIO Input Data
Register
Function
S_CLKOUT[0]
disable
S_CLKOUT[1]
disable
Type
R/WC
R/WS
R/WC
R/WS
R/O
R/O
Type
R/W
R/W
Page 92 of 114
Description
Setting any of these bits to 1 drives the corresponding bits LOW on the
GPIO[3:0] bus if it is programmed as bi-directional. Data is driven on the
PCI clock cycle following completion of the configuration write to this
register. The bit positions corresponding to the GPIO pins that are
programmed as input only are not driven. Writing 0 to theses bits has no
effect and will return the last written value when read. Bits [11:8]
correspond to GPIO [3:0].
Reset to 0
Setting any of these bits to 1 drives the corresponding bits HIGH on the
GPIO[3:0] bus if it is programmed as bi-directional. Data is driven on the
PCI clock cycle following completion of the configuration write to this
register. The bit positions corresponding to the GPIO pins that are
programmed as input only are not driven. Writing 0 to theses bits has no
effect and will return the last written value when read. Bits [15:12]
correspond to GPIO [3:0].
Reset to 0
Setting any of these bits to 1 configures the corresponding bits on the
GPIO[3:0] bus as input only. As a result, the output driver is tri-stated.
Writing 0 to theses bits has no effect and will return the last written value
when read. Bits [19:16] correspond to GPIO [3:0].
Reset to 0
Setting any of these bits to 1 configures the corresponding bits on the
GPIO[3:0] bus as bi-directional; the output driver is enabled and drives
the value set in the output data register (offset 65h). Writing 0 to theses
bits has no effect and will return the last written value when read. Bits
[23:20] correspond to GPIO [3:0].
Reset to 0
Returns 0 when read. Reset to 0
Contains the state of the GPIO[3:0] pins. State is updated on the PCI
clock cycle after any change to the state of the GPIO[3:0] pins.
Reset to 0.
Description
S_CLKOUT[0] (slot 0) Enable
00: enable S_CLKOUT[0]
01: enable S_CLKOUT[0]
10: enable S_CLKOUT[0]
11: disable S_CLKOUT[0] and driven HIGH
Reset to 00
S_CLKOUT[1] (slot 1) Enable
00: enable S_CLKOUT[1]
01: enable S_CLKOUT[1]
10: enable S_CLKOUT[1]
11: disable S_CLKOUT[1] and driven HIGH
Reset to 00
ASYNCHRONOUS 2-PORT
DEC 2009 REVISION 1.02
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A