LM5117PMH/NOPB National Semiconductor, LM5117PMH/NOPB Datasheet - Page 13

• Manufacturer Part Number: LM5117PMH/NOPB
• Description: IC BUCK CONTROLLER 20-TSSOP
• Manufacturer: National Semiconductor
• Series: -r

Specifications of LM5117PMH/NOPB

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 530kHz
• Duty Cycle: 95%
• Voltage - Supply: 5.5 V ~ 65 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-TSSOP (0.173", 4.40mm Width) Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

For 14.5V <V
ed by using a series Zener diode from the output to VCC.
In high input voltage applications, extra care should be taken
to ensure the VIN pin does not exceed the absolute maximum
voltage rating of 75V. During line or load transients, voltage
ringing on the VIN that exceeds the Absolute Maximum Rat-
ing can damage the IC. Both careful PC board layout and the
use of quality bypass capacitors located close to the VIN and
AGND pin are essential. Adding an R-C filter (R
VIN is optional and helps to prevent faulty operation caused
by poor PC board layout and high frequency switching noise
injection. The recommended capacitance and resistance
range are 0.1µF to 10µF and 1Ω to 10Ω.
UVLO
The LM5117 contains a dual level UVLO (under-voltage lock-
out) circuit. When the UVLO is less than 0.4V, the LM5117 is
in shutdown mode. The shutdown comparator provides
100mV of hysteresis to avoid chatter during transitions. When
the UVLO pin voltage is greater than 0.4V but less than 1.25V,
the controller is in standby mode. In the standby mode, the
VCC bias regulator is active but the HO and LO drivers are
disabled and the SS pin is held low. This feature allows the
UVLO pin to be used as a remote shutdown function by pulling
the UVLO pin down below 0.4V with an external open collec-
tor or open drain device. When the VCC pin exceeds its
under-voltage lockout threshold and the UVLO pin voltage is
greater than 1.25V, the HO and LO drivers are enabled and
normal operation begins.
The UVLO pin should not be left floating. An external UVLO
set-point voltage divider from the VIN to AGND is used to set
FIGURE 5. External VCC Supply for 14.5V <V
OUT
FIGURE 6. UVLO Configuration
, the external supply voltage can be regulat-
VIN
, C
OUT
30143259
VIN
30143268
) on
13
the minimum input operating voltage of the regulator. The di-
vider must be designed such that the voltage at the UVLO pin
is greater than 1.25V and never exceeds 15V when the input
voltage is in the desired operating range. If necessary, the
UVLO pin can be clamped with a Zener diode.
UVLO hysteresis is accomplished with an internal 20μA cur-
rent source that is switched on or off into the impedance of
the UVLO set-point divider. When the UVLO pin voltage ex-
ceeds the 1.25V threshold, the current source is enabled to
quickly raise the voltage at the UVLO pin. When the UVLO
pin voltage falls below the 1.25V threshold, the current source
is disabled causing the voltage at the UVLO pin to quickly fall.
The use of a C
imize switching noise injection into UVLO pin, but it may slow
down the falling speed of the UVLO pin when the 20μA current
source is disabled. The recommended range for C
to 220pF.
The values of R
lowing equations:
Where V
V
during turn-on.
Oscillator and Sync Capability
The LM5117 switching frequency is programmed by a single
external resistor connected between the RT pin and the
AGND pin. The resistor should be located very close to the
device and connected directly to the RT and AGND pins. To
set a desired switching frequency (f
be calculated from the following equation:
The RT pin can be used to synchronize the internal oscillator
to an external clock. The internal oscillator can be synchro-
nized by AC coupling a positive edge into the RT pin. The
voltage at the RT pin is nominally 1.25V and the voltage at
the RT pin must exceed the RT Sync Positive Threshold to
trip the internal synchronization pulse detector. A 5V ampli-
tude pulse signal coupled through 100pF capacitor is a good
starting point. The frequency of the external synchronization
pulse is recommended to be within +/-10% of the frequency
programmed by the RT resistor but will operate to +100/-40%
of the programmed frequency. Care should be taken to guar-
antee that the RT pin voltage does not go below -0.3V at the
falling edge of the external pulse. This may limit the duty cycle
of external synchronization pulse.
The R
free running or externally synchronized.
IN(STARTUP)
T
resistor is always required, whether the oscillator is
HYS
is the desired startup voltage of the regulator
FT
UV1
is the desired UVLO hysteresis and
capacitor in parallel with R
and R
UV2
can be determined from the fol-
SW
), the resistor value can
UV1
helps to min-
www.national.com
FT
is 10pF
(1)
(2)
(3)