LM5117PMH/NOPB National Semiconductor, LM5117PMH/NOPB Datasheet - Page 24

• Manufacturer Part Number: LM5117PMH/NOPB
• Description: IC BUCK CONTROLLER 20-TSSOP
• Manufacturer: National Semiconductor
• Series: -r

Specifications of LM5117PMH/NOPB

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 530kHz
• Duty Cycle: 95%
• Voltage - Supply: 5.5 V ~ 65 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-TSSOP (0.173", 4.40mm Width) Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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The standard value of 165 kΩ was selected for R
UVLO DIVIDER R
The desired startup voltage and the hysteresis are set by the
voltage divider R
ing for the divider. For this design, the startup voltage was set
to 14V, 1V below V
R
follows:
The standard value of 100kΩ was selected for R
selected to be 9.76kΩ. A value of 47pF was chosen for C
VCC DISABLE AND EXTERNAL VCC SUPPLY
The 12V output voltage allows the external VCC supply con-
figuration as shown in
be left floating since V
point level.
POWER SWITCHES Q
Selection of the power NMOS devices is governed by the
same trade-offs as switching frequency. Breaking down the
losses in the high-side and low-side NMOS devices is one
way to compare the relative efficiencies of different devices.
Losses in the power NMOS devices can be broken down into
conduction loss, gate charging loss, and switching loss.
Conduction loss P
Where D is the duty cycle and the factor of 1.3 accounts for
the increase in the NMOS device on-resistance due to heat-
ing. Alternatively, the factor of 1.3 can be eliminated and the
high temperature on-resistance of the NMOS device can be
estimated using the R
MOSFET datasheet.
Gate charging loss (P
gate capacitance of the power NMOS devices and is approx-
imated as:
Qg refers to the total gate charge of an individual NMOS de-
vice, and ‘n’ is the number of NMOS devices. Gate charge
loss differs from conduction and switching losses in that the
actual dissipation occurs in the controller IC. Switching loss
(P
NMOS device turns on and off. During the transition period
both current and voltage are present in the channel of the
NMOS device. The switching loss can be approximated as:
UV1
SW
, R
) occurs during the brief transition period as the high-side
UV2
can be calculated from equations (1) and (2) as
UV1
UV2
DC
IN(MIN)
and R
is approximately:
, R
GC
Figure
OUT
DS(ON)
H
UV1
) results from the current driving the
. V
and Q
is higher than VCC regulator set-
UV2
AND C
HYS
3. In this example, VCCDIS can
vs Temperature curves in the
. Capacitor C
L
was set to 2V. The value of
FT
FT
provides filter-
UV2
RAMP
. R
UV1
.
was
FT
.
24
t
device. The rise and fall times are usually mentioned in the
MOSFET datasheet or can be empirically observed with an
oscilloscope. Switching loss is calculated for the high-side
NMOS device only. Switching loss in the low-side NMOS de-
vice is negligible because the body diode of the low-side
NMOS device turns on before and after the low-side NMOS
device switches. For this example, the maximum drain-to-
source voltage applied to either NMOS device is 55V. The
selected NMOS devices must be able to withstand 55V plus
any ringing from drain to source and must be able to handle
at least the VCC voltage plus any ringing from gate to source.
SNUBBER COMPONENTS R
A resistor-capacitor snubber network across the low-side
NMOS device reduces ringing and spikes at the switching
node. Excessive ringing and spikes can cause erratic opera-
tion and can couple noise to the output voltage. Selecting the
values for the snubber is best accomplished through empirical
methods. First, make sure the lead lengths for the snubber
connections are very short. Start with a resistor value be-
tween 5 and 50Ω. Increasing the value of the snubber capac-
itor results in more damping, but higher snubber losses.
Select a minimum value for the snubber capacitor that pro-
vides adequate damping of the spikes on the switch waveform
at heavy load. A snubber may not be necessary with an op-
timized layout.
BOOTSTRAP CAPACITOR C
D
The bootstrap capacitor between the HB and SW pin supplies
the gate current to charge the high-side NMOS device gate
during each cycle’s turn-on and also supplies recovery charge
for the bootstrap diode. These current peaks can be several
amperes. The recommended value of the bootstrap capacitor
is at least 0.1μF. C
ramic capacitor located at the pins of the IC to minimize
potentially damaging voltage transients caused by trace in-
ductance. The absolute minimum value for the bootstrap
capacitor is calculated as:
Where Qg is the high-side NMOS gate charge and ΔV
the tolerable voltage droop on C
5% of VCC or 0.15V conservatively. A value of 0.47μF was
selected for this design.
VCC CAPACITOR C
The primary purpose of the VCC capacitor (C
the peak transient currents of the LO driver and bootstrap
diode as well as provide stability for the VCC regulator. These
peak currents can be several amperes. The recommended
value of C
be a good quality, low ESR, ceramic capacitor. C
be placed at the pins of the IC to minimize potentially dam-
aging voltage transients caused by trace inductance. A value
of 1μF was selected for this design.
OUTPUT CAPACITOR C
The output capacitors smooth the output voltage ripple
caused by inductor ripple current and provide a source of
charge during transient loading conditions. For this design
R
HB
and t
F
are the rise and fall times of the high-side NMOS
VCC
should be no smaller than 0.47μF, and should
HB
VCC
should be a good quality, low ESR, ce-
O
SNB
HB
HB
AND BOOTSTRAP DIODE
, which is typically less than
AND C
SNB
VCC
) is to supply
VCC
should
HB
is